encounter preroute timing 分析时的错误求助
时间：10-02
整理：3721RD
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encounter preroute timing 分析时报以下错误，说路径没有定义，但是在constraint文件里已经定义了啊
**ERROR: (TA-152):A latency path from the 'Fall' edge of the master clockat source pin 'u_aes_core_top/u_S65NLLPLL_ZP1500/CLK_OUT' to the 'Fall' edge of generated clock 'aes_clk' at pin 'u_aes_core_top/u_divider/aes_mux/Z' cannot be found. You must modify your create_generated_clock constraint to be consistent with the network topology. The analysis will continue using 0ns source latency for generated clock 'aes_clk'. For backward compatibility with earlier releases or to remove the edge-to-edge sufficiency checking, you should set the global 'timing_enable_genclk_edge_based_source_latency' to false
constraint中的定义：
create_generated_clock [get_pins u_aes_core_top/u_divider/aes_mux/Z]-name aes_clk-source [get_pins u_aes_core_top/u_S65NLLPLL_ZP1500/CLK_OUT]-divide_by 1
**ERROR: (TA-152):A latency path from the 'Fall' edge of the master clockat source pin 'u_aes_core_top/u_S65NLLPLL_ZP1500/CLK_OUT' to the 'Fall' edge of generated clock 'aes_clk' at pin 'u_aes_core_top/u_divider/aes_mux/Z' cannot be found. You must modify your create_generated_clock constraint to be consistent with the network topology. The analysis will continue using 0ns source latency for generated clock 'aes_clk'. For backward compatibility with earlier releases or to remove the edge-to-edge sufficiency checking, you should set the global 'timing_enable_genclk_edge_based_source_latency' to false
constraint中的定义：
create_generated_clock [get_pins u_aes_core_top/u_divider/aes_mux/Z]-name aes_clk-source [get_pins u_aes_core_top/u_S65NLLPLL_ZP1500/CLK_OUT]-divide_by 1
检查source与mux/Z之间的连接，是否真的存在，或者被case analysis挡住了
不会检查，不过还是谢谢了。
佩服你的诚实和勇气！
代码中看看，有没有这个路径，或者路径的hier层级错误了
Refer below link,
Good explanantion
http://www.cadence.com/Community/forums/p/13859/1292970.aspx
Thanks.
太感谢6楼提供的网页了，终于解决了。
我的问题是 generate_clock定义的时钟下降沿的时刻 和 分频器电路里面实际的产生下降沿的时刻是不统一的。
所以把DC综合脚本里面的 create_generated_clock -name divCLK96M-source LPWIFI_TXCLK288M-edges {1 3 7}
把edges的数值修改成 和 分频器电路产生的下降沿时刻统一，就解决了
或者set_global 'timing_enable_genclk_edge_based_source_latency'false也行的