DPLL

“The DPLL is used to run the MPEG-2 decoder without an external VCXO. Only a simple 27.0MHz crystal is

used to synchronise the MPEG decoder to the MPEG encoder. Synchronisation is required to avoid buffer

over- or underflow. The digital PLL functionality is realised in order to insert or remove one eighth of the clock

period (DELTA) of the 391.5MHz. A register defines how often one DELTA will be inserted or removed. This

down counter is running at 65.25MHz and, when it reaches zero, one DELTA will be inserted to the 391.5MHz

clock period or one DELTA will be removed from the clock period.”

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