怎样对有pad的设计进行DFT综合

我的例化了pad的top模块
`include "test.v"
module pad_test(
clk,
res,
a,
scan_en,
b
);
input clk;
input res;
input scan_en;
input[2:0] a;
output[2:0] b;
wire[2:0] a_core;
wire[2:0] b_core;
wire clk_core;
wire res_core;
wire scan_en_core;

PIB1 pad_clk (.INCORE(clk_core),.PAD(clk));
PIB1 pad_res (.INCORE(res_core),.PAD(res));
PIB1 pad_a0 (.INCORE(a_core[0]),.PAD(a[0]));
PIB1 pad_a1 (.INCORE(a_core[1]),.PAD(a[1]));
PIB1 pad_a2 (.INCORE(a_core[2]),.PAD(a[2]));
PIB1 pad_scan_en (.INCORE(scan_en_core),.PAD(scan_en));
POT16 pad_b0 (.PAD(b[0]),.OUTCORE(b_core[0]));
POT16 pad_b1 (.PAD(b[1]),.OUTCORE(b_core[1]));
POT16 pad_b2 (.PAD(b[2]),.OUTCORE(b_core[2]));
test test(
.clk(clk_core),
.res(res_core),
.a(a_core),
.b(b_core),
.scan_en(scan_en_core)
);
endmodule
在进行DFT综合时，插入扫描链
set_dft_signal -view existing_dft -type ScanClock -timing {45 55} -port clk
set_dft_signal -view existing_dft -port res -type Reset -active_state 1
set_dft_signal -view existing_dft -port scan_en -type ScanEnable -active_state 1
set_dft_insertion_configuration -preserve_design_name true ;# no change to design names
set_scan_configuration -chain_count 1 -clock_mixing mix_clocks
set_dft_signal -view spec -type ScanDataIn -port a[0]
set_dft_signal -view spec -type ScanDataOut -port b[2]
set_scan_path chain1 -view spec -scan_data_in a[0]-scan_data_out b[2]
报出两种violations
1.res ( Warning: Clock res cannot capture data with other clocks off. (D8-1) )
2.DFF set/reset line not controlled
这是怎么个情况啊?求解呀

你怎么办呢?