DC综合之后做PT 为什么静态时序仿真的结果不同

DC综合时设置了一个分频时钟clk2create_clock-period 6.0-waveform "0 3.0" [get_ports clk]
create_generated_clock -name clk2 -source [get_pins cd0/clk2_reg/clocked_on] -divide_by 2 [get_pins cd0/clk2_reg/Q]
DC综合的结果并不涉及clk2，将DC产生的netlist放到PT中做时序分析，得到的结果却有clk2的违例，为什么clk2的违例在DC中没有说明呢?
=======================DC 结果===================================================
Operating Conditions: slowLibrary: slow
Wire Load Model Mode: top
Startpoint: B21/cnt_reg
(rising edge-triggered flip-flop clocked by clk)
Endpoint: B21/out0_reg[50]
(rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Des/Clust/PortWire Load ModelLibrary
------------------------------------------------
PCS_22tsmc18_wl20slow
PointIncrPath
-----------------------------------------------------------
clock clk (rise edge)0.000.00
clock network delay (ideal)0.600.60
B21/cnt_reg/CK (JKFFSXL)0.000.60 r
B21/cnt_reg/Q (JKFFSXL)0.971.57 f
U6101/Y (INVX4)2.133.71 r
U6151/Y (INVX8)0.974.67 f
U6138/Y (CLKINVX3)1.065.73 r
U6630/Y (AOI22X1)0.336.06 f
B21/out0_reg[50]/D (DFFSXL)0.006.06 f
data arrival time6.06
clock clk (rise edge)6.006.00
clock network delay (ideal)0.606.60
clock uncertainty-0.206.40
B21/out0_reg[50]/CK (DFFSXL)0.006.40 r
library setup time-0.276.13
data required time6.13
-----------------------------------------------------------
data required time6.13
data arrival time-6.06
-----------------------------------------------------------
slack (MET)0.07
================================================================================


============================PT 结果===============================================
pt_shell> report_timing -significant_digits 3
****************************************
Report : timing
-path_type full
-delay_type max
-max_paths 1
Design : PCS_22
Version: D-2010.06
Date: Mon Jul7 10:54:39 2014
****************************************

Startpoint: rst (input port)
Endpoint: D_f1_a2_out_reg
(recovery check against rising-edge clock clk)
Path Group: **async_default**
Path Type: max
PointIncrPath
---------------------------------------------------------------
clock (input port clock) (rise edge)0.0000.000
input external delay0.0000.000 r
rst (in)0.0000.000 r
D_f1_a2_out_reg/SN (DFFSX2)0.0000.000 r
data arrival time0.000
clock clk (rise edge)6.0006.000
clock network delay (ideal)0.6006.600
clock uncertainty-0.2006.400
D_f1_a2_out_reg/CK (DFFSX2)6.400 r
library recovery time-0.0056.395
data required time6.395
---------------------------------------------------------------
data required time6.395
data arrival time0.000
---------------------------------------------------------------
slack (MET)6.395

Startpoint: B21_cnt_reg
(rising edge-triggered flip-flop clocked by clk)
Endpoint: B21_out0_reg_50_
(rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
PointIncrPath
---------------------------------------------------------------
clock clk (rise edge)0.0000.000
clock network delay (ideal)0.6000.600
B21_cnt_reg/CK (JKFFSXL)0.0000.600 r
B21_cnt_reg/Q (JKFFSXL)0.973 *1.573 f
U6101/Y (INVX4)2.134 *3.707 r
U6151/Y (INVX8)0.968 *4.675 f
U6138/Y (CLKINVX3)1.058 *5.733 r
U6630/Y (AOI22X1)0.333 *6.066 f
B21_out0_reg_50_/D (DFFSXL)0.000 *6.066 f
data arrival time6.066
clock clk (rise edge)6.0006.000
clock network delay (ideal)0.6006.600
clock uncertainty-0.2006.400
B21_out0_reg_50_/CK (DFFSXL)6.400 r
library setup time-0.270 *6.130
data required time6.130
---------------------------------------------------------------
data required time6.130
data arrival time-6.066
---------------------------------------------------------------
slack (MET)0.064

Startpoint: hs0_H2_H9_en2_reg_0_
(rising edge-triggered flip-flop clocked by clk2)
Endpoint: hs0_H2_H9_outb_reg_27_
(rising edge-triggered flip-flop clocked by clk2)
Path Group: clk2
Path Type: max
PointIncrPath
---------------------------------------------------------------
clock clk2 (rise edge)0.0000.000
clock network delay (ideal)0.3000.300
hs0_H2_H9_en2_reg_0_/CK (DFFSX1)0.0000.300 r
hs0_H2_H9_en2_reg_0_/QN (DFFSX1)1.536 *1.836 f
U6292/Y (INVX1)2.426 *4.262 r
U6291/Y (CLKINVX3)2.104 *6.366 f
U6290/Y (NOR3X1)2.782 *9.148 r
U6071/Y (CLKBUFX8)1.733 *10.881 r
U7488/Y (AOI22X1)0.483 *11.364 f
U7489/Y (OAI21XL)0.465 *11.829 r
U7490/Y (AOI21X1)0.264 *12.093 f
hs0_H2_H9_outb_reg_27_/D (DFFSX1)0.000 *12.093 f
data arrival time12.093
clock clk2 (rise edge)12.00012.000
clock network delay (ideal)0.30012.300
hs0_H2_H9_outb_reg_27_/CK (DFFSX1)12.300 r
library setup time-0.340 *11.960
data required time11.960
---------------------------------------------------------------
data required time11.960
data arrival time-12.093
---------------------------------------------------------------
slack (VIOLATED)-0.133

===============================================================================

顶一下自己！

DC 的 report header 呢?

不太明白你的问题什么意思，很明显clk2所在路径组有时序违反，时序违反量很小，可以放在后端pr去修。DC后的网表就拿去做PT结果几乎一样稍微有一点不同。

首先谢谢您的回答 我的意思是为什么DC中分频时钟CLK2没有出现report_timing -group clk2 时居然没有与clk2相关的路径

那就是在DC中没有clk2的路径组而在PT中有，那说明分频时钟定义成功。那你先用report_clock查看分频时钟主时钟和分频时钟，然后利用report_timing不加任何选项，来生成每一个路径组的WNS时序报告，看这个里面是否有clk2路径组

谢谢您的回答 问题已经解决了 在DC中我编译直接用的 compile -ultra 可能是这个原因导致综合的过程没有考虑分频时钟；
在脚本中的我在这条语句之前加了 compile -map_effort high

反正最后综合出来的结果是有关clk2的，深层次的原因我也不太清楚