为什么在PT中报出的路径在ICC中找不到呢？求助

现在的情况是这样的，相同的路径在DCT中也可以报出来的，用DDC传给ICC后，在ICC中打开做个init design就已经报不出来这个路径了，到底是错在哪里了呢?

report 呢

can you show the report and let us check this issues?

****************************************
Report : timing
-path full
-delay max
-max_paths 1
Design : cluster_6
Version: I-2013.12
Date: Wed Mar5 23:55:06 2014
****************************************
* Some/all delay information is back-annotated.
Operating Conditions: NCCOMLibrary: tcbn65gpluslvttc_ccs
Startpoint: procA_inst_reg_addr_reg_1_
(rising edge-triggered flip-flop clocked by clk)
Endpoint: procB_inst_wrap_inst_fifo_inst_mem_inst_clk_gate_inst6_u_ICG
(gating element for clock clk)
Path Group: clk
Path Type: max
PointIncrPath
--------------------------------------------------------------------------
clock clk (rise edge)0.000.00
clock network delay (ideal)0.100.10
procA_inst_reg_addr_reg_1_/CP (EDFCNQD2LVT)
0.000.10 r
procA_inst_reg_addr_reg_1_/Q (EDFCNQD2LVT)
0.100.20 r
U78036/ZN (IND2D4LVT)0.02 *0.22 f
U68345/ZN (NR3D8LVT)0.02 *0.24 r
U137851/ZN (ND2D4LVT)0.02 *0.26 f
U6907/ZN (CKND8LVT)0.02 *0.28 r
U6913/ZN (CKND16LVT)0.02 *0.30 f
U170200/ZN (NR2XD3LVT)0.02 *0.33 r
U170203/Z (AO22D2LVT)0.04 *0.36 r
inner_node_000_inst_U34/Z (CKMUX2D1)0.04 *0.41 r
U33094/Z (BUFFD8LVT)0.04 *0.45 r
U6065/Z (MUX2D4LVT)0.05 *0.50 r
U166450/Z (CKBD16LVT)0.04 *0.54 r
U187262/Z (MUX2D4LVT)0.06 *0.61 r
U141638/Z (CKBD16LVT)0.04 *0.65 r
U36655/ZN (ND2D4LVT)0.05 *0.70 f
U71349/ZN (ND2D8LVT)0.03 *0.73 r
U187329/Z (AN2D4)0.05 *0.78 r
U78106/Z (AN2D4LVT)0.03 *0.81 r
U117485/ZN (ND2D1LVT)0.02 *0.83 f
U96875/ZN (CKND2LVT)0.02 *0.85 r
U97005/ZN (ND2D3LVT)0.02 *0.87 f
U97180/ZN (NR2XD1LVT)0.05 *0.92 r
U197807/Z (BUFFD2LVT)0.04 *0.96 r
U197808/ZN (CKND2LVT)0.02 *0.98 f
U97291/ZN (ND2D1LVT)0.02 *1.01 r
procB_inst_wrap_inst_fifo_inst_mem_inst_clk_gate_inst6_u_ICG/E (CKLNQD4LVT)
0.00 *1.01 r
data arrival time1.01
clock clk (rise edge)1.111.11
clock network delay (ideal)0.101.21
clock uncertainty-0.151.06
procB_inst_wrap_inst_fifo_inst_mem_inst_clk_gate_inst6_u_ICG/CP (CKLNQD4LVT)
0.001.06 r
clock gating setup time-0.051.01
data required time1.01
--------------------------------------------------------------------------
data required time1.01
data arrival time-1.01
--------------------------------------------------------------------------
slack (MET)0.01
这个是在DCT中给出的报告，之后把DCT的ddc sdc给ICC后从ICC中往后面做，做完之后report timing，相同的路径报了No paths

用timing analysis window可以么?

ICC 有对 clock gating check 做什么 special setting 吗
report 一下以 "procB_inst_wrap_inst_fifo_inst_mem_inst_clk_gate_inst6_u_ICG/E" 为 end point 的所有的 path

问题找到了，是由于ICC自动断了一些arc去break loop正好断到了报告的路径，现在的问题在
http://bbs.eetop.cn/thread-438716-1-1.html

问题找到了，是由于ICC自动断了一些arc去break loop正好断到了报告的路径，现在的问题在
http://bbs.eetop.cn/thread-438716-1-1.html