为什么同样一条路径，iCC与PT结果不同？

ICC: Startpoint: u_bt_ctrl_logic/u_bit_ctrl/rp_enable_d1_reg
(rising edge-triggered flip-flop clocked by i_ps_clk)
Endpoint: u_bt_ctrl_logic/u_bit_ctrl/rp_enable_d2_reg
(rising edge-triggered flip-flop clocked by i_ps_clk)
Scenario: func_wcl_c
Path Group: i_ps_clk
Path Type: min
PointIncrPathVoltage
------------------------------------------------------------------------------------
clock i_ps_clk (rise edge)0.000.00
clock network delay (ideal) 0.000.00
u_bt_ctrl_logic/u_bit_ctrl/rp_enable_d1_reg/CK (DFFRPQ_X0P5M_A9TR40)
0.000.00 r0.99
u_bit_ctrl_logic/u_bit_ctrl/rp_enable_d1_reg/Q (DFFRPQ_X0P5M_A9TR40)
0.130.13 f0.99
u_bit_ctrl_logic/u_bit_ctrl/rp_enable_d2_reg/D (DFFRPQ_X0P5M_A9TR40)
0.00 &0.13 f0.99
data arrival time0.13
clock i_ps_clk (rise edge)0.000.00
clock network delay (ideal)0.000.00
clock uncertainty0.050.05
u_bit_ctrl_logic/u_bit_ctrl/rp_enable_d2_reg/CK (DFFRPQ_X0P5M_A9TR40)
0.000.05 r
library hold time0.110.16
data required time0.16
------------------------------------------------------------------------------------
data required time0.16
data arrival time-0.13
------------------------------------------------------------------------------------
slack (VIOLATED)-0.04

PT:
Startpoint: u_bt_ctrl_logic/u_bit_ctrl/rp_enable_d1_reg
(rising edge-triggered flip-flop clocked by i_ps_clk)
Endpoint: u_bit_ctrl_logic/u_bit_ctrl/rp_enable_d2_reg
(rising edge-triggered flip-flop clocked by i_ps_clk)
Path Group: i_ps_clk
Path Type: min
Scenario: func_wcl_c
PointIncrPath
------------------------------------------------------------------------------
clock i_ps_clk (rise edge)0.000.00
clock network delay (propagated) 0.190.19
u_bit_ctrl_logic/u_bit_ctrl/rp_enable_d1_reg/CK (DFFRPQ_X0P5M_A9TR40)
0.000.19 r
u_bit_ctrl_logic/u_bit_ctrl/rp_enable_d1_reg/Q (DFFRPQ_X0P5M_A9TR40)
0.10 &0.28 f
u_bit_ctrl_logic/u_bit_ctrl/rp_enable_d2_reg/D (DFFRPQ_X0P5M_A9TR40)
0.00 &0.28 f
data arrival time0.28
clock i_ps_clk (rise edge)0.000.00
clock network delay (propagated)0.200.20
clock uncertainty0.050.25
u_bit_ctrl_logic/u_bit_ctrl/rp_enable_d2_reg/CK (DFFRPQ_X0P5M_A9TR40)
0.25 r
library hold time0.000.25
data required time0.25
------------------------------------------------------------------------------
data required time0.25
data arrival time-0.28
------------------------------------------------------------------------------
slack (MET)0.03

不理解的是为什么icc的clk 是ideal的，我是ICC布局布线后report_timng的。

这个问题看来得小编出面帮忙解答了

ideal vs propagated ?
check "set_ideal_network" & "set_propagated_clock" in the sdc file~

你在ICC report_timing 之前 请设置 set_propagated_clock [all_clocks]

首先感谢楼上二位的回复。当前进展如下：
1.与set_propagated_clock关系不大，因为icc 中cts后，built clock are propagateed automaticaly
2.我做了实验，原因是report_timing，我增加了-scenario [all_scenarios]选项，因为该项目工艺是40nm ，需要考虑mcmm。如果去掉该选项，则无ideal clk
3.-scenario [all_scenarios] 选项是要加上的，原因我在进一步去学习。

我记得有个帖子好像说过，因为算法不一样

那个，如果一样pt就不用卖了，不过可以人为的根据实际情况调整icc的rc抽出，让结果更好的保持一致

执行MCMM，某个scenario中的clock为ideal。需要在所有的scenario中执行一遍set_propagated_clock [all_clocks]