Formality error

各位，下面是一段formality的verify report,
reference:RTL
Implementation: Synthesis netlist
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Reference design: r:/WORK/digtop
Implementation design: i:/WORK/digtop
1585 Passing compare points
5 Failing compare points
91 Aborted compare points
0 Unverified compare points
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Matched Compare PointsBBPinLoopBBNetCutPortDFFLATTOTAL
----------------------------------------------------------------------------------------
Passing (equivalent)72200160134381585
Failing (not equivalent)05000005
Aborted
Loop(cycle-driven)02700064091
Not Compared
Unread0000035035
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因为Combination Loop, FV failed, 后仿无论function, timing都没有问题。请问我可以忽略这种错误吗?

每人遇到过这种问题么?

我想的是FM就是用来验证功能是否正确，只要后方功能和时序都下正确，其实都可以不必做形式验证了。

加入 SVF文件试试?或者用LEC试试?
形式验证不过，心理总是不踏实。