最近做单元包特征化遇到的问题····跪求大神···
Celltemplate file
* Generated by Liberty NCX vC-2009.06-SP1
cell_footprint : SRMCML_AND2 ;
area : 15.141525 ;
rail_connection : VDD VDD ;
rail_connection : VFN VFN ;
rail_connection : VFP VFP ;
pin A {
direction : input ;
capacitance : 0.002576;
input_signal_level: VDD ;
}
pin B {
direction : input ;
capacitance : 0.002576;
input_signal_level : VDD ;
}
pin OUT {
direction : output ;
function : "(A&B)" ;
output_signal_level : VDD ;
ncx_internal_power_rise_input_transition_time_index : 0 ;
ncx_internal_power_fall_input_transition_time_index : 0 ;
ncx_internal_power_rise_total_output_net_capacitance_index : 0 ;
ncx_internal_power_fall_total_output_net_capacitance_index : 0 ;
ncx_rise_input_net_transition_index : 0 ;
ncx_fall_input_net_transition_index : 0 ;
ncx_rise_total_output_net_capacitance_index : 0 ;
ncx_fall_total_output_net_capacitance_index : 0 ;
}
pg_pin VDD {
voltage_name: VDD ;
pg_type: primary_power ;
}
pg_pin VFN {
voltage_name: VFN ;
pg_type: backup_power ;
}
pg_pin VFP {
voltage_name: VFP ;
pg_type: backup_power ;
}
pg_pin VSS {
voltage_name: VSS ;
pg_type: primary_ground ;
}
ncx_optimization {
}
Librarytemplate file
* Generated by Liberty NCX vC-2009.06-SP1
include srmcml_stdcell.indexes ;
power_supply{
default_power_rail:VDD ;
power_rail: VDD 1.20000 ;
power_rail: VFN 0.50000 ;
power_rail: VFP 0.10000 ;
power_rail: VSS 0.00000 ;
}
ncx_create_arcs : SRMCML_OR2 * *leakage_power states all ;
do {
SRMCML_AND2
}
Ncx-runfile
#########################################################################
set input_library
./input_lib/srmcml_stdcell.lib
set output_library
./out_lib/SRMCML.lib
set log_file
./log_out/ncx.log
set model_file
./model/model.typ
set work_dir
./work
set netlist_dir
./netlist
set netlist_suffix
.spc
set simulator_exec
/home/tools/synopsys/hspice_vC-2009.09/hspice/linux/hspice
set templates
true
set output_templates
true
set compact
false
set timing_arcs_to_template
true
set sensitization_to_template
true
set preanalysis_opt
false
set sensitization_to_library
false
set driver_waveform_to_library
false
set use_driver_waveform_from_library
false
set only_active_cells_to_library
false
#Timing and Power settings
set timing
true
set ccs_timing
false
set compact_timing
false
set nldm
true
set nlpm
true
set power
true
set ccs_power
false
set ncx_use_pg_pins
false
set compact_power
false
set variation_leakage
true
#Template settings
set input_template_dir
./config
set template_suffix
.opt
set precision
5
set output_template_dir
./work
set farm_type
NoFarm
set prechar
false
#################################################
SeedLibrary file
/* table model: cell-delay */
library(smcml_stdcell) {
/*general attributes */
delay_model : table_lookup;
in_place_swap_mode : match_footprint;
library_features(report_delay_calculation);
/*documentation attributes */
revision : 1.0;
date : "Tue Jan 25 10:17:44 2005";
comment : "Copyright (c) 2005 Artisan Components, Inc.
All Rights Reserved.";
/*unit attributes */
time_unit : "1ns";
voltage_unit : "1V";
current_unit : "1mA";
pulling_resistance_unit : "1kohm";
leakage_power_unit : "1pW";
capacitive_load_unit (1.0,pf);
/*operation conditions */
nom_process
: 1;
nom_temperature : 25;
nom_voltage
: 1.2;
ncx_use_pg_pins : false ;
output_signal_level_low
: 0.99 ;
output_signal_level_high : 1.1 ;
operating_conditions(smcml_stdcell) {
process
: 1;
temperature
: 25;
voltage
: 1.2;
tree_type
:"balanced_tree" ;
}
default_operating_conditions : smcml_stdcell;
/*threshold definitions */
slew_lower_threshold_pct_fall : 30.0;
slew_upper_threshold_pct_fall : 70.0;
slew_lower_threshold_pct_rise : 30.0;
slew_upper_threshold_pct_rise : 70.0;
input_threshold_pct_fall
:50.0;
input_threshold_pct_rise
:50.0;
output_threshold_pct_fall
:60.0;
output_threshold_pct_rise
:60.0;
slew_derate_from_library
:1.0;
/*default attributes */
default_leakage_power_density
:0.0;
default_cell_leakage_power
:0.0;
default_fanout_load
: 1.0;
default_output_pin_cap
: 0.0;
default_inout_pin_cap
:0.00158;
default_input_pin_cap
:0.00158;
default_max_transition
: 1.02;
/*templates */
lu_table_template(delay_template_7x1) {
variable_1 : input_net_transition;
index_1 ("1000, 1001, 1002, 1003, 1004, 1005, 1006");
}
power_lut_template(energy_template_7x1) {
variable_1 : input_transition_time;
index_1("1000, 1001, 1002, 1003, 1004, 1005, 1006");
}
lu_table_template(delay_template_7x7) {
variable_1 : input_net_transition;
variable_2 : total_output_net_capacitance;
index_1 ("1000, 1001, 1002, 1003, 1004, 1005, 1006");
index_2 ("1000, 1001, 1002, 1003, 1004, 1005, 1006");
}
power_lut_template(energy_template_7x7) {
variable_1 : input_transition_time;
variable_2 : total_output_net_capacitance;
index_1 ("1000, 1001, 1002, 1003, 1004, 1005, 1006");
index_2 ("1000, 1001, 1002, 1003, 1004, 1005, 1006");
}
power_lut_template(energy_template_1x7) {
variable_1 : total_output_net_capacitance;
index_1 ("1000, 1001, 1002, 1003, 1004, 1005, 1006");
}
power_lut_template(energy_template_7x3x3) {
variable_1 : input_transition_time;
variable_2 : total_output_net_capacitance;
variable_3 : equal_or_opposite_output_net_capacitance;
index_1 ("1000, 1001, 1002, 1003, 1004, 1005, 1006");
index_2 ("1000, 1001, 1002");
index_3 ("1000, 1001, 1002");
}
power_lut_template(passive_energy_template_1x7) {
variable_1 : input_transition_time;
index_1 ("1000, 1001, 1002, 1003, 1004, 1005, 1006");
}
lu_table_template(setup_template_3x3) {
variable_1 : constrained_pin_transition;
variable_2 : related_pin_transition;
index_1 ("1000, 1001, 1002");
index_2 ("1000, 1001, 1002");
}
lu_table_template(hold_template_3x3) {
variable_1 : constrained_pin_transition;
variable_2 : related_pin_transition;
index_1 ("1000, 1001, 1002");
index_2 ("1000, 1001, 1002");
}
lu_table_template(recovery_template_3x3) {
variable_1 : constrained_pin_transition;
variable_2 : related_pin_transition;
index_1 ("1000, 1001, 1002");
index_2 ("1000, 1001, 1002");
}
lu_table_template(removal_template_3x3){
variable_1 : constrained_pin_transition;
variable_2 : related_pin_transition;
index_1 ("1000, 1001, 1002");
index_2 ("1000, 1001, 1002");
}
lu_table_template(minpw-active_template_1x7) {
variable_1 : related_pin_transition;
index_1 ("1000, 1001, 1002, 1003, 1004, 1005, 1006");
}
lu_table_template(minpw-inactive_template_1x7) {
variable_1 : related_pin_transition;
index_1 ("1000, 1001, 1002, 1003, 1004, 1005, 1006");
}
/*k-factors */
k_process_cell_leakage_power
: 0;
k_temp_cell_leakage_power
: 0;
k_volt_cell_leakage_power
:0;
k_process_internal_power
: 0;
k_temp_internal_power
: 0;
k_volt_internal_power
: 0;
k_process_rise_transition
: 1;
k_temp_rise_transition
: 0;
k_volt_rise_transition
: 0;
k_process_fall_transition
: 1;
k_temp_fall_transition
: 0;
k_volt_fall_transition
: 0;
k_process_setup_rise
: 1;
k_temp_setup_rise
: 0;
k_volt_setup_rise
: 0;
k_process_setup_fall
: 1;
k_temp_setup_fall
: 0;
k_volt_setup_fall
: 0;
k_process_hold_rise
: 1;
k_temp_hold_rise
: 0;
k_volt_hold_rise
: 0;
k_process_hold_fall
: 1;
k_temp_hold_fall
: 0;
k_volt_hold_fall
: 0;
k_process_min_pulse_width_high
:1;
k_temp_min_pulse_width_high
: 0;
k_volt_min_pulse_width_high
: 0;
k_process_min_pulse_width_low
:1;
k_temp_min_pulse_width_low
: 0;
k_volt_min_pulse_width_low
:0;
k_process_recovery_rise
: 1;
k_temp_recovery_rise
: 0;
k_volt_recovery_rise
: 0;
k_process_recovery_fall
: 1;
k_temp_recovery_fall
: 0;
k_volt_recovery_fall
: 0;
k_process_cell_rise
: 1;
k_temp_cell_rise
: 0;
k_volt_cell_rise
: 0;
k_process_cell_fall
: 1;
k_temp_cell_fall
: 0;
k_volt_cell_fall
: 0;
k_process_wire_cap
: 0;
k_temp_wire_cap
: 0;
k_volt_wire_cap
: 0;
k_process_wire_res
: 0;
k_temp_wire_res
: 0;
k_volt_wire_res
: 0;
k_process_pin_cap
: 0;
k_temp_pin_cap
: 0;
k_volt_pin_cap
: 0;
/*pad attributes */
output_voltage(GENERAL) {
vol
: 0.9;
voh
: VDD - 0.1;
vomin
:-0.5;
vomax
: VDD + 0.5;
}
input_voltage(CMOS) {
vil
:
0.3 * VDD ;
vih
:
0.7 * VDD ;
vimin
: -0.5;
vimax
: VDD + 0.5;
}
input_voltage(TTL) {
vil
: 0.8;
vih
: 2;
vimin
: -0.5;
vimax
: VDD + 0.5;
}
/* wire-loads */
wire_load("smic13_wl10") {
resistance
: 8.5e-8;
capacitance
: 1.5e-4;
area
: 0.7;
slope
: 66.667;
fanout_length
(1,66.667);
}
wire_load("smic13_wl20") {
resistance
: 8.5e-8;
capacitance
: 1.5e-4;
area
: 0.7;
slope
: 133.334;
fanout_length
(1,133.334);
}
wire_load("smic13_wl30") {
resistance
: 8.5e-8;
capacitance
: 1.5e-4;
area
: 0.7;
slope
: 200.001;
fanout_length
(1,200.001);
}
wire_load("smic13_wl40") {
resistance
: 8.5e-8;
capacitance
: 1.5e-4;
area
: 0.7;
slope
: 266.668;
fanout_length
(1,266.668);
}
wire_load("smic13_wl50") {
resistance
: 8.5e-8;
capacitance
: 1.5e-4;
area
: 0.7;
slope
: 333.335;
fanout_length
(1,333.335);
}
/*QA wire-load */
wire_load("ForQA") {
resistance
: 0;
capacitance
: 1;
area
: 1;
slope
: 1;
fanout_length(1,0);
fanout_length(10,0);
}
}
Ncx.logfile
Liberty NCX (TM) C-2009.06-SP1
Synopsys Inc. Proprietaryand Confidential
Your use of this program and its documentation are covered by a license
agreement, a copy of which may be found in the file"license.txt"
located in the install directory. Your use of this program is your
consent to be bound by its terms and conditions.
Parts of this program are protected by law and international treaties.
Unpublished - Copyright (c) 2006 Synopsys Inc.
All rights reserved.
Allrights for unpublished material are reserved under U.S. copyright laws.
Copyright notice is precautionary and doesnot imply publication or disclosure.
Liberty NCX is a Trademark ofSynopsys Inc.
Build date: Jul 16 2009
Local host: eda.cise Linux (2.6.9-67.ELsmp)(i686 X 8)
Command-line: ncx \
-frun
Process id: 13298
activating CCS power for VA-leakagegeneration
Program configuration:
Files/folders:
input_library
:/home/stu/xxc/SRMCML/input_lib/srmcml_stdcell.lib (user)
output_library
:/home/stu/xxc/SRMCML/out_lib/SRMCML.lib (user)
log_file
:/home/stu/xxc/SRMCML/log_out/ncx.log (user)
work_dir
:/home/stu/xxc/SRMCML/work (user)
Flows:
preanalysis_opt
: false (user)
prechar
: false (user)
timing
: true (user)
power
: true (user)
noise
: false
compact
: false (user)
templates
: true (user)
ibis
: false
Simulation settings:
simulator_exec
:/home/tools/synopsys/hspice_vC-2009.09/hspice/linux/hspice (user)
simulator_type
: hspice
model_file
:/home/stu/xxc/SRMCML/model/model.typ (user)
netlist_dir
: /home/stu/xxc/SRMCML/netlist(user)
netlist_suffix
: .spc (user)
simulation_dir
:/home/stu/xxc/SRMCML
Compute farm:
farm_type
: NoFarm(user)
queue_name
: normal
project_name
: NcxProj
bundle_size
: 50
constraint_bundle_size: 10
max_jobs
: 100
max_job_time
: 600
update_interval
: 60
farm_retry_limit
: 3
farm_retry_interval : 3
model_extraction_to_farm: false
backup_failed_sims
: false
Outputformat control:
precision
: 5 (user)
only_active_cells_to_library: false (user)
failed_cells_to_library: false
sensitization_to_library: false (user)
driver_waveform_to_library: false (user)
use_driver_waveform_from_library: false (user)
Program control:
autofix
: true
fix_nldm_timing
: delay
cleanup
: 1
reuse
: false
test_simulator
: true
Timing model acquisition options:
ccs_timing
: false (user)
compact_timing
: false (user)
nldm
: true (user)
capacitance
: true
delay
: true
constraint
: true
shpr_constraint
: false
design_rules
: false
max_capacitance
: true
max_transition
: true
variation
: false
mismatch
: false
Power model acquisition options:
ccs_power
: true (user)
compact_power
: false (user)
nlpm
: true (user)
variation_leakage
: true (user)
Template usage options:
input_template_dir
:/home/stu/xxc/SRMCML/config (user)
output_template_dir : /home/stu/xxc/SRMCML/work (user)
template_suffix
: .opt (user)
timing_arcs_to_template: true (user)
sensitization_to_template: true (user)
Thu Mar 14 15:52:41 2013
--- begin flow...
--- testing simulation setup...
using HSPICE -- C-2009.09 32-BIT (Aug 242009)
done
reading library/home/stu/xxc/SRMCML/input_lib/srmcml_stdcell.lib...done
initializing database...
reading/home/stu/xxc/SRMCML/config/srmcml_stdcell.opt...
reading/home/stu/xxc/SRMCML/config/srmcml_stdcell.indexes...done
do 4 cells...done
Warning: CCS power requires pg_pin syntax,set ncx_use_pg_pins to true.
adding new cell SRMCML_AND2
reading/home/stu/xxc/SRMCML/config/SRMCML_AND2.opt...done
adding new cell SRMCML_AND3
reading/home/stu/xxc/SRMCML/config/SRMCML_AND3.opt...done
adding new cell SRMCML_INV
reading/home/stu/xxc/SRMCML/config/SRMCML_INV.opt...done
adding new cell SRMCML_OR2
reading/home/stu/xxc/SRMCML/config/SRMCML_OR2.opt...done
Warning: output_voltage GENERAL attributevoh has invalid type (expression). (NCXDB-224)
Warning: output_voltage GENERAL attributevomax has invalid type (expression). (NCXDB-224)
Warning: Invalid specification for voltagegroup GENERAL.
Warning: input_voltage CMOS attribute vilhas invalid type (expression). (NCXDB-224)
Warning: input_voltage CMOS attribute vihhas invalid type (expression). (NCXDB-224)
Warning: input_voltage CMOS attribute vimaxhas invalid type (expression). (NCXDB-224)
Warning: Invalid specification for voltagegroup CMOS.
Warning: input_voltage TTL attribute vimaxhas invalid type (expression). (NCXDB-224)
Warning: Invalid specification for voltagegroup TTL.
cell types:
combinational
: 4
done
Thu Mar 14 15:52:41 2013
--- generating sensitizations...
cell smcml_stdcell::SRMCML_AND2 (1 of 4) (2in/1out pins)
creating delay arcs...
combinational (positive_unate) A -> OUT
combinational (positive_unate) B -> OUT
2 delay arcs created
cell smcml_stdcell::SRMCML_AND3 (2 of 4) (3in/1out pins)
creating delay arcs...
combinational (positive_unate) A -> OUT
combinational (positive_unate) B -> OUT
combinational (positive_unate) C -> OUT
3 delay arcs created
cell smcml_stdcell::SRMCML_INV (3 of 4) (1in/1out pins)
creating delay arcs...
combinational (negative_unate) IN -> OUT
1 delay arcs created
cell smcml_stdcell::SRMCML_OR2 (4 of 4) (2in/1out pins)
creating delay arcs...
combinational (positive_unate) A -> OUT
combinational (positive_unate) B -> OUT
2 delay arcs created
done
Thu Mar 14 15:52:41 2013
--- checking indices and signal levels...
Checking va_parameters_leakage ...
Copying va_parameters_leakage fromva_parameters ...
Copying va_parameters_leakage fromva_parameters ...
Copying va_parameters_leakage fromva_parameters ...
Copying va_parameters_leakage fromva_parameters ...
done
Thu Mar 14 15:52:41 2013
--- building netlists for nominal analysis...
cell smcml_stdcell::SRMCML_AND2 (1 of 4) ()
building non-propagated power netlists...
building dc leakage power netlists...
cell smcml_stdcell::SRMCML_AND3 (2 of 4) ()
building non-propagated power netlists...
building dc leakage power netlists...
cell smcml_stdcell::SRMCML_INV (3 of 4) ()
building non-propagated power netlists...
building dc leakage power netlists...
cell smcml_stdcell::SRMCML_OR2 (4 of 4) ()
building non-propagated power netlists...
building dc leakage power netlists...
done
Thu Mar 14 15:52:42 2013
--- checking nominal simulation status...
queued=48 done=0
queued=47 done=0
queued=46 done=0
queued=45 done=0
queued=44 done=0
queued=43 done=0
queued=42 done=0
queued=41 done=0
[1/48] SRMCML_AND2::A pA_0005r.sp
[2/48] SRMCML_AND2::A pA_0006f.sp
[3/48] SRMCML_AND2::B pB_0001r.sp
[4/48] SRMCML_AND2::B pB_0002f.sp
[5/48] SRMCML_AND2::BdSRMCML_AND2_0004.sp
Warning: multiple openchannels from OUT -> pwr/gnd in intrinsic_parasitic group
Warning: saving only theminimum resistance channel
[6/48] SRMCML_AND2::B dSRMCML_AND2_0001.sp
Warning: multiple open channels from OUT-> pwr/gnd in intrinsic_parasitic group
Warning: saving only the minimum resistancechannel
[7/48] SRMCML_AND2::B dSRMCML_AND2_0002.sp
Warning: multiple open channels from OUT-> pwr/gnd in intrinsic_parasitic group
Warning: saving only the minimum resistancechannel
[8/48] SRMCML_AND2::BdSRMCML_AND2_0003.sp
Warning: multiple openchannels from OUT -> pwr/gnd in intrinsic_parasitic group
Warning: saving only theminimum resistance channel
Warning: IntrinsicCapacitance for VSS is less than zero
[9/48]SRMCML_AND2::combinational arc [0] A -> OUT f () tOUT_A_0000f.sp
Warning: [7] inslew:1.2e-11 load: 4.266e-14: CCS delay error 8.57595e-12 (2.43552% > tol 2%)
Warning: [21] inslew:4.4e-11 load: 4.266e-14: CCS delay error 6.90006e-12 (2.10729% > tol 2%)
Warning: [29] inslew:1.38e-10 load: 3.95e-16: current peak occurs at end of current segment
netlist:/home/stu/xxc/SRMCML/smcml_stdcell/SRMCML_AND2/tOUT_A_0000f/tOUT_A_0000f.sp
re-simulating with runlvl=6
[10/49] SRMCML_AND2::combinational arc [1]B -> OUT f () tOUT_B_0001f.sp
Warning: [1] inslew: 1.2e-11 load:3.95e-16: current peak occurs at end of current segment
netlist: /home/stu/xxc/SRMCML/smcml_stdcell/SRMCML_AND2/tOUT_B_0001f/tOUT_B_0001f.sp
re-simulating with runlvl=6
[11/50] SRMCML_AND2::combinational arc [1]B -> OUT r () tOUT_B_0001r.sp
Warning: [50] inslew: 1.02e-09 load:3.95e-16: CCS delay error 3.84706e-10 (20.9765% > tol 2%)
Warning: [51] inslew: 1.02e-09 load:1.027e-15: CCS delay error 3.90275e-10 (21.0323% > tol 2%)
netlist:/home/stu/xxc/SRMCML/smcml_stdcell/SRMCML_AND2/tOUT_B_0001r/tOUT_B_0001r.sp
re-simulating with runlvl=6
[12/51] SRMCML_AND3::A pA_0017r.sp
[13/51] SRMCML_AND3::A pA_0018f.sp
[14/51] SRMCML_AND3::B pB_0009r.sp
[15/51] SRMCML_AND2::combinational arc [0]A -> OUT r () tOUT_A_0000r.sp
netlist:/home/stu/xxc/SRMCML/smcml_stdcell/SRMCML_AND2/tOUT_A_0000r/tOUT_A_0000r.sp
re-simulating with runlvl=6
[16/52] SRMCML_AND3::B pB_0010f.sp
[17/52] SRMCML_AND3::C pC_0001r.sp
[18/52] SRMCML_AND3::C pC_0002f.sp
[19/52] SRMCML_AND3::C dSRMCML_AND3_0001.sp
Warning: multiple open channels from OUT-> pwr/gnd in intrinsic_parasitic group
Warning: saving only the minimum resistancechannel
Warning: Intrinsic Capacitance for VSS isless than zero
[20/52] SRMCML_AND3::C dSRMCML_AND3_0002.sp
Warning: multiple open channels from OUT-> pwr/gnd in intrinsic_parasitic group
Warning: saving only the minimum resistancechannel
Warning: Intrinsic Capacitance for VSS isless than zero
[21/52] SRMCML_AND3::C dSRMCML_AND3_0003.sp
Warning: multiple open channels from OUT-> pwr/gnd in intrinsic_parasitic group
Warning: saving only the minimum resistancechannel
Warning: Intrinsic Capacitance for VSS isless than zero
[22/52] SRMCML_AND3::C dSRMCML_AND3_0004.sp
Warning: multiple open channels from OUT-> pwr/gnd in intrinsic_parasitic group
Warning: saving only the minimum resistancechannel
Warning: Intrinsic Capacitance for VSS isless than zero
[23/52] SRMCML_AND3::C dSRMCML_AND3_0005.sp
Warning: multiple open channels from OUT-> pwr/gnd in intrinsic_parasitic group
Warning: saving only the minimum resistancechannel
Warning: Intrinsic Capacitance for VSS isless than zero
[24/52] SRMCML_AND3::C dSRMCML_AND3_0006.sp
Warning: multiple open channels from OUT-> pwr/gnd in intrinsic_parasitic group
Warning: saving only the minimum resistancechannel
Warning: Intrinsic Capacitance for VSS isless than zero
[25/52] SRMCML_AND3::C dSRMCML_AND3_0007.sp
Warning: multiple open channels from OUT-> pwr/gnd in intrinsic_parasitic group
Warning: saving only the minimum resistancechannel
[26/52] SRMCML_AND3::C dSRMCML_AND3_0008.sp
Warning: multiple open channels from OUT-> pwr/gnd in intrinsic_parasitic group
Warning: saving only the minimum resistancechannel
Warning: Intrinsic Capacitance for VSS isless than zero
[27/52] SRMCML_AND3::combinational arc [0]A -> OUT f () tOUT_A_0000f.sp
Warning: [3] inslew: 1.2e-11 load:2.37e-15: current peak occurs at end of current segment
netlist: /home/stu/xxc/SRMCML/smcml_stdcell/SRMCML_AND3/tOUT_A_0000f/tOUT_A_0000f.sp
re-simulating with runlvl=6
[28/53] SRMCML_AND3::combinational arc [1]B -> OUT f () tOUT_B_0001f.sp
Warning: [3] inslew: 1.2e-11 load:2.37e-15: current peak occurs at end of current segment
netlist: /home/stu/xxc/SRMCML/smcml_stdcell/SRMCML_AND3/tOUT_B_0001f/tOUT_B_0001f.sp
re-simulating with runlvl=6
[29/54] SRMCML_AND3::combinational arc [0]A -> OUT r () tOUT_A_0000r.sp
netlist:/home/stu/xxc/SRMCML/smcml_stdcell/SRMCML_AND3/tOUT_A_0000r/tOUT_A_0000r.sp
re-simulating with runlvl=6
[30/55] SRMCML_AND3::combinational arc [2]C -> OUT f () tOUT_C_0002f.sp
Warning: [24] inslew: 7.6e-11 load:2.37e-15: current peak occurs at end of current segment
netlist: /home/stu/xxc/SRMCML/smcml_stdcell/SRMCML_AND3/tOUT_C_0002f/tOUT_C_0002f.sp
re-simulating with runlvl=6
[31/56] SRMCML_INV::IN dSRMCML_INV_0002.sp
Warning: Intrinsic Capacitance for VSS isless than zero
[32/56] SRMCML_INV::IN dSRMCML_INV_0001.sp
Warning: multiple open channels from OUT-> pwr/gnd in intrinsic_parasitic group
Warning: saving only the minimum resistancechannel
Warning: Intrinsic Capacitance for VSS isless than zero
[33/56] SRMCML_AND3::combinational arc [1]B -> OUT r () tOUT_B_0001r.sp
netlist:/home/stu/xxc/SRMCML/smcml_stdcell/SRMCML_AND3/tOUT_B_0001r/tOUT_B_0001r.sp
re-simulating with runlvl=6
[34/57] SRMCML_OR2::A pA_0007r.sp
[35/57] SRMCML_AND3::combinational arc [2]C -> OUT r () tOUT_C_0002r.sp
netlist:/home/stu/xxc/SRMCML/smcml_stdcell/SRMCML_AND3/tOUT_C_0002r/tOUT_C_0002r.sp
re-simulating with runlvl=6
[36/58] SRMCML_OR2::A pA_0008f.sp
[37/58] SRMCML_INV::combinational arc [0]IN -> OUT r () tOUT_IN_0000r.sp
Warning: [44] inslew: 5.16e-10 load:1.027e-15: CCS delay error 2.53806e-10 (195.848% > tol 2%)
Error: Can't perform CCS Timing segment, inraw data at least needs 3 points (NCXMD-28)
Error: Error computing threshold crossingtime in CCS waveform (NCXMD-25)
netlist:/home/stu/xxc/SRMCML/smcml_stdcell/SRMCML_INV/tOUT_IN_0000r/tOUT_IN_0000r.sp
re-simulating with runlvl=6
[38/59] SRMCML_INV::combinational arc [0]IN -> OUT f () tOUT_IN_0000f.sp
Error: Can't perform CCS Timing segment, inraw data at least needs 3 points (NCXMD-28)
Error: Error computing threshold crossingtime in CCS waveform (NCXMD-25)
netlist: /home/stu/xxc/SRMCML/smcml_stdcell/SRMCML_INV/tOUT_IN_0000f/tOUT_IN_0000f.sp
re-simulating with runlvl=6
[39/60] SRMCML_OR2::B pB_0003r.sp
[40/60] SRMCML_OR2::B pB_0004f.sp
[41/60] SRMCML_OR2::B dSRMCML_OR2_0001.sp
Warning: multiple open channels from OUT-> pwr/gnd in intrinsic_parasitic group
Warning: saving only the minimum resistancechannel
Warning: Intrinsic Capacitance for VSS isless than zero
[42/60] SRMCML_OR2::combinational arc [0] A-> OUT r () tOUT_A_0000r.sp
Error: Can't perform CCS Timing segment, inraw data at least needs 3 points (NCXMD-28)
Error: Error computing threshold crossingtime in CCS waveform (NCXMD-25)
netlist: /home/stu/xxc/SRMCML/smcml_stdcell/SRMCML_OR2/tOUT_A_0000r/tOUT_A_0000r.sp
re-simulating with runlvl=6
[43/61] SRMCML_OR2::B dSRMCML_OR2_0003.sp
Warning: multiple open channels from OUT-> pwr/gnd in intrinsic_parasitic group
Warning: saving only the minimum resistancechannel
Warning: Intrinsic Capacitance for VSS isless than zero
[44/61] SRMCML_OR2::B dSRMCML_OR2_0002.sp
Warning: multiple open channels from OUT-> pwr/gnd in intrinsic_parasitic group
Warning: saving only the minimum resistancechannel
[45/61] SRMCML_OR2::combinational arc [1] B-> OUT r () tOUT_B_0001r.sp
Error: Can't perform CCS Timing segment, inraw data at least needs 3 points (NCXMD-28)
Error: Error computing threshold crossingtime in CCS waveform (NCXMD-25)
netlist: /home/stu/xxc/SRMCML/smcml_stdcell/SRMCML_OR2/tOUT_B_0001r/tOUT_B_0001r.sp
re-simulating with runlvl=6
[46/62] SRMCML_OR2::B dSRMCML_OR2_0004.sp
Warning: multiple open channels from OUT-> pwr/gnd in intrinsic_parasitic group
Warning: saving only the minimum resistancechannel
Warning: Intrinsic Capacitance for VSS isless than zero
[47/62] SRMCML_OR2::combinational arc [1] B-> OUT f () tOUT_B_0001f.sp
Error: Can't perform CCS Timing segment, inraw data at least needs 3 points (NCXMD-28)
Error: Error computing threshold crossingtime in CCS waveform (NCXMD-25)
netlist: /home/stu/xxc/SRMCML/smcml_stdcell/SRMCML_OR2/tOUT_B_0001f/tOUT_B_0001f.sp
re-simulating with runlvl=6
[48/63] SRMCML_OR2::combinational arc [0] A-> OUT f () tOUT_A_0000f.sp
Error: Can't perform CCS Timing segment, inraw data at least needs 3 points (NCXMD-28)
Error: Error computing threshold crossingtime in CCS waveform (NCXMD-25)
netlist: /home/stu/xxc/SRMCML/smcml_stdcell/SRMCML_OR2/tOUT_A_0000f/tOUT_A_0000f.sp
re-simulating with runlvl=6
[49/64] SRMCML_AND2::combinational arc [0]A -> OUT f () tOUT_A_0000f.sp
Warning: [7] inslew: 1.2e-11 load:4.266e-14: CCS delay error 9.16412e-12 (2.60119% > tol 2%)
Warning: [12] inslew: 2.8e-11 load:1.0428e-14: CCS delay error 2.24855e-12 (3.36583% > tol 2%)
Warning: [36] inslew: 2.64e-10 load:3.95e-16: current peak occurs at end of current segment
netlist: /home/stu/xxc/SRMCML/smcml_stdcell/SRMCML_AND2/tOUT_A_0000f/tOUT_A_0000f.sp
using max accuracy results available
[50/64] SRMCML_AND2::combinational arc [1]B -> OUT f () tOUT_B_0001f.sp
Warning: [29] inslew: 1.38e-10 load:3.95e-16: current peak occurs at end of current segment
netlist: /home/stu/xxc/SRMCML/smcml_stdcell/SRMCML_AND2/tOUT_B_0001f/tOUT_B_0001f.sp
using max accuracy results available
[51/64] SRMCML_AND3::combinational arc [0]A -> OUT f () tOUT_A_0000f.sp
Warning: [3] inslew: 1.2e-11 load:2.37e-15: current peak occurs at end of current segment
netlist: /home/stu/xxc/SRMCML/smcml_stdcell/SRMCML_AND3/tOUT_A_0000f/tOUT_A_0000f.sp
using max accuracy results available
[52/64] SRMCML_AND3::combinational arc [1]B -> OUT f () tOUT_B_0001f.sp
Warning: [3] inslew: 1.2e-11 load:2.37e-15: current peak occurs at end of current segment
netlist: /home/stu/xxc/SRMCML/smcml_stdcell/SRMCML_AND3/tOUT_B_0001f/tOUT_B_0001f.sp
using max accuracy results available
[53/64] SRMCML_AND2::combinational arc [1]B -> OUT r () tOUT_B_0001r.sp
netlist:/home/stu/xxc/SRMCML/smcml_stdcell/SRMCML_AND2/tOUT_B_0001r/tOUT_B_0001r.sp
using max accuracy results available
[54/64] SRMCML_AND3::combinational arc [2]C -> OUT f () tOUT_C_0002f.sp
Warning: [24] inslew: 7.6e-11 load:2.37e-15: current peak occurs at end of current segment
netlist: /home/stu/xxc/SRMCML/smcml_stdcell/SRMCML_AND3/tOUT_C_0002f/tOUT_C_0002f.sp
using max accuracy results available
[55/64] SRMCML_AND2::combinational arc [0]A -> OUT r () tOUT_A_0000r.sp
netlist:/home/stu/xxc/SRMCML/smcml_stdcell/SRMCML_AND2/tOUT_A_0000r/tOUT_A_0000r.sp
using max accuracy results available
[56/64] SRMCML_AND3::combinational arc [0]A -> OUT r () tOUT_A_0000r.sp
netlist:/home/stu/xxc/SRMCML/smcml_stdcell/SRMCML_AND3/tOUT_A_0000r/tOUT_A_0000r.sp
using max accuracy results available
[57/64]SRMCML_INV::combinational arc [0] IN -> OUT f () tOUT_IN_0000f.sp
Error: Can't perform CCSTiming segment, in raw data at least needs 3 points (NCXMD-28)
Error: Error computingthreshold crossing time in CCS waveform (NCXMD-25)
netlist:/home/stu/xxc/SRMCML/smcml_stdcell/SRMCML_INV/tOUT_IN_0000f/tOUT_IN_0000f.sp
using max accuracy results available
[58/64] SRMCML_INV::combinational arc [0]IN -> OUT r () tOUT_IN_0000r.sp
[59/64] SRMCML_AND3::combinational arc [1]B -> OUT r () tOUT_B_0001r.sp
netlist: /home/stu/xxc/SRMCML/smcml_stdcell/SRMCML_AND3/tOUT_B_0001r/tOUT_B_0001r.sp
using max accuracy results available
[60/64] SRMCML_OR2::combinational arc [1] B-> OUT r () tOUT_B_0001r.sp
Error: Can't perform CCS Timing segment, inraw data at least needs 3 points (NCXMD-28)
Error: Error computing threshold crossingtime in CCS waveform (NCXMD-25)
netlist:/home/stu/xxc/SRMCML/smcml_stdcell/SRMCML_OR2/tOUT_B_0001r/tOUT_B_0001r.sp
using max accuracy results available
[61/64] SRMCML_OR2::combinational arc [0] A-> OUT r () tOUT_A_0000r.sp
[62/64] SRMCML_AND3::combinational arc [2]C -> OUT r () tOUT_C_0002r.sp
netlist:/home/stu/xxc/SRMCML/smcml_stdcell/SRMCML_AND3/tOUT_C_0002r/tOUT_C_0002r.sp
using max accuracy results available
[63/64] SRMCML_OR2::combinational arc [1] B-> OUT f () tOUT_B_0001f.sp
Error: Can't perform CCS Timing segment, inraw data at least needs 3 points (NCXMD-28)
Error: Error computing threshold crossingtime in CCS waveform (NCXMD-25)
netlist: /home/stu/xxc/SRMCML/smcml_stdcell/SRMCML_OR2/tOUT_B_0001f/tOUT_B_0001f.sp
using max accuracy results available
[64/64] SRMCML_OR2::combinational arc [0] A-> OUT f () tOUT_A_0000f.sp
Error: Can't perform CCS Timing segment, inraw data at least needs 3 points (NCXMD-28)
Error: Error computing threshold crossingtime in CCS waveform (NCXMD-25)
netlist: /home/stu/xxc/SRMCML/smcml_stdcell/SRMCML_OR2/tOUT_A_0000f/tOUT_A_0000f.sp
using max accuracy results available
done
Thu Mar 14 15:52:49 2013
--- extracting default arcs...
done
total model extraction time: 1.663 seconds(elapsed)
Thu Mar 14 15:52:49 2013
--- merging library...done
Thu Mar 14 15:52:49 2013
writing/home/stu/xxc/SRMCML/work/SRMCML.opt...done
Thu Mar 14 15:52:49 2013
--- deleting sensitization templates...done
Thu Mar 14 15:52:49 2013
Checking semantics...1...2...done
writing smcml_stdcell to/home/stu/xxc/SRMCML/out_lib/SRMCML.lib...
done
Thu Mar 14 15:52:49 2013
done
total program time
: 7.583 seconds (0.13 min.)
主要的错误就是红色的字体·····虽然太多了···还希望大神···拯救拯救小弟啊····小弟都要抑郁死了····
大神来拯救小弟吧
在来顶顶啊