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帮忙看一下LVS错误报告呗~~~

时间:10-02 整理:3721RD 点击:
Error:Different numbers of ports (see below).
Error:Ground net missing in layout.
LAYOUT CELL NAME:good
SOURCE CELL NAME:good
--------------------------------------------------------------------------------------------------------------
INITIAL NUMBERS OF OBJECTS
--------------------------
LayoutSourceComponent Type
--------------------------
Ports:2425*
Nets:892972*
Instances:879865*MN (4 pins)
901871*MP (4 pins)
------------
Total Inst:17801736

NUMBERS OF OBJECTS AFTER TRANSFORMATION
---------------------------------------
LayoutSourceComponent Type
--------------------------
Ports:2425*
Nets:509592*
Instances:55MN (4 pins)
44MP (4 pins)
04*SPDW_2_1 (4 pins)
01*SPDW_2_1_1 (5 pins)
40*SPMN_2_1 (5 pins)
10*SPMN_2_1_1 (6 pins)
11SPMP_2_1 (5 pins)
77SPMP_2_2 (6 pins)
11SPMP_3_1_1 (7 pins)
11SPMN((2+1)*1) (6 pins)
33SPMP((2+1)*1) (6 pins)
108108_invb (6 pins)
328334*_invv (4 pins)
41*_invx2v (4 pins)
33_invx3v (4 pins)
3838_nand2v (5 pins)
66_nor2v (5 pins)
66_nor3v (6 pins)
4444_sdw2v (4 pins)
5353_smn3v (5 pins)
3232_smp2v (4 pins)
5252_smp3v (5 pins)
1111_tgmb (7 pins)
11_xori2v (5 pins)
------------
Total Inst:713716

* = Number of objects in layout different from number in source.

**************************************************************************************************************
INFORMATION AND WARNINGS
**************************************************************************************************************

o Statistics:
84 layout mos transistors were reduced to 24.
60 mos transistors were deleted by parallel reduction.
20 source mos transistors were reduced to 4.
16 mos transistors were deleted by parallel reduction.

**************************************************************************************************************
SUMMARY
**************************************************************************************************************
Total CPU Time:0 sec
Total Elapsed Time:0 sec
最近学习数字后端,想走一遍流程,结果LVS出现错误。
SOURCE 25个端口很奇怪 一共就24个ports(不算电源)
我要是给layout打上VDD VSS的label后,就26个ports,还是对不上。麻烦给看看问题出现在哪 没有啥头绪啊。

字层是否用对,是否只识别顶层字,connect open net等

怎么没有port的详细内容

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