lvs加急求助

各位大侠，项目快要流片了，物理验证时遇到问题，难以解决，加急求助。
我们用的是华虹.13工艺，标准单元里有vpb和vnb两个pin,vpb通过阱区连到tapcell上，然后连到power（vpwr）上，vnb在衬底上，应该连得是ground(vgnd)，但是版图里抽出的.sp中pmos和nmos的b端都连到了power上，现在找不到他们是怎么连到一起的。附上report，在线等。
report:
INCORRECT NETS
DISC#LAYOUT NAMESOURCE NAME
**************************************************************************************************************
1Net VPWR** no similar net **
--- Devices on layout net VPWR ---
(cell ports)(cell ports)
X: XX: X
D1: D1D1: D1
C1: C1C1: C1
B1: B1B1: B1
A1: A1A1: A1
A2: A2A2: A2
VPWR: VPWR** no similar net **
** no similar net **VPWR: VPWR
** no similar net **VGND: VGND
M11(3.605,1.835)MP(PHIGHVT)MMPA1MP(PHIGHVT)
g: A2g: A2
d: 11d: pndA
s: VPWR** no similar net **
b: VPWR** no similar net **
** no similar net **s: VPWR
** no similar net **b: VPB
M10(3.175,1.835)MP(PHIGHVT)MMPA0MP(PHIGHVT)
g: A1g: A1
s: 11d: pndA
d: VPWR** no similar net **
b: VPWR** no similar net **
** no similar net **s: VPWR
** no similar net **b: VPB
M9(2.405,1.835)MP(PHIGHVT)MMPB0MP(PHIGHVT)
g: B1g: B1
s: 13d: pndB
d: 11s: pndA
b: VPWR** no similar net **
** no similar net **b: VPB
M8(1.865,1.835)MP(PHIGHVT)MMPC0MP(PHIGHVT)
g: C1g: C1
s: 12d: pndC
d: 13s: pndB
b: VPWR** no similar net **
** no similar net **b: VPB
M7(1.475,1.835)MP(PHIGHVT)MMPD0MP(PHIGHVT)
g: D1g: D1
s: 10d: y
d: 12s: pndC
b: VPWR** no similar net **
** no similar net **b: VPB
M6(0.525,1.835)MP(PHIGHVT)MMIPXMP(PHIGHVT)
g: 10g: y
s: Xd: X
d: VPWR** no similar net **
b: VPWR** no similar net **
** no similar net **s: VPWR
** no similar net **b: VPB
M5(3.575,0.245)MN(NSHORT)MMNA1MN(NSHORT)
g: A2g: A2
s: 14d: sndA1
d: VPWR** no similar net **
b: VPWR** no similar net **
** no similar net **s: VGND
** no similar net **b: VNB
M4(3.215,0.245)MN(NSHORT)MMNA0MN(NSHORT)
g: A1g: A1
s: 10d: y
d: 14s: sndA1
b: VPWR** no similar net **
** no similar net **b: VNB
M3(2.405,0.245)MN(NSHORT)MMNB0MN(NSHORT)
g: B1g: B1
d: 10d: y
s: VPWR** no similar net **
b: VPWR** no similar net **
** no similar net **s: VGND
** no similar net **b: VNB
M2(1.865,0.245)MN(NSHORT)MMNC0MN(NSHORT)
g: C1g: C1
s: 10d: y
d: VPWR** no similar net **
b: VPWR** no similar net **
** no similar net **s: VGND
** no similar net **b: VNB
M1(1.435,0.245)MN(NSHORT)MMND0MN(NSHORT)
g: D1g: D1
d: 10d: y
s: VPWR** no similar net **
b: VPWR** no similar net **
** no similar net **s: VGND
** no similar net **b: VNB
M0(0.565,0.245)MN(NSHORT)MMINXMN(NSHORT)
g: 10g: y
s: Xd: X
d: VPWR** no similar net **
b: VPWR** no similar net **
** no similar net **s: VGND
** no similar net **b: VNB

*.connect

标准单元里有vpb和vnb两个pin，修改成对应的pwr/GND就行

derive pg connection