STA时，门控时钟违例问题

Startpoint: ee_interface/eeclk_en_reg
(rising edge-triggered flip-flop clocked by CLK8)
Endpoint: ee_interface/U338
(falling clock gating-check end-point clocked by CLK8')
Path Group: **clock_gating_default**
Path Type: min
PointIncrPath
------------------------------------------------------------------------------
clock CLK8 (rise edge)0.0000.000
clock network delay (ideal)0.0000.000
ee_interface/eeclk_en_reg/CK (DFFRHQX1)0.0000.000 r
ee_interface/eeclk_en_reg/Q (DFFRHQX1) <-0.2700.270 f
ee_interface/U339/A (INVX1) <-0.0000.270 f
ee_interface/U339/Y (INVX1) <-0.0980.368 r
ee_interface/U338/B (NOR2X1)0.0000.368 r
data arrival time0.368
clock CLK8' (rise edge)295.000295.000
clock network delay (ideal)0.000295.000
clock uncertainty0.200295.200
ee_interface/U338/A (NOR2X1)295.200 r
clock gating hold time0.000295.200
data required time295.200
------------------------------------------------------------------------------
data required time295.200
data arrival time-0.368
------------------------------------------------------------------------------
slack (VIOLATED)-294.832
图中白线经过的路径为pt报告中分析的门控时钟的路径。时钟周期为590，请大伙帮着分析下怎样解决这个问题。

这种门控要么set false path，要么改用ICG单元

report里面的clock CLK8' 应该是falling edge 吧?
应该是需要multicycle的。

首先再次谢谢陈哥，怎样改用ICG单元呢，以前没有接触过。下面的代码是否可以在设计中生成ICG单元呢?
#Set clock gating options, max_fanout default is unlimited
set_clock_gating_style -sequential_cell latch \
-positive_edge_logic {integrated} \
-control_point before \
-control_signal scan_enable
#Create a more balanced clock tree by inserting “always enabled” ICGs
set power_cg_all_registers true
set power_remove_redundant_clock_gates true
read_verilogdesign.v
current_design top
link
#Insert clock gating
insert_clock_gating
compile
#Generate a report on clock gating inserted
report_clock_gating

就是那几个命令