后端对scan_chain的处理问题？
时间：10-02
整理：3721RD
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各位大牛好，经常在公司的招聘信息上看到要求有关DFT的知识和经验，比如下面的一则招聘信息：
1.MSEE with 3+ years or Bachelor with 5+ years of industrial experience in ASICdesign
2. Expertise in place and routing, signal integrity, power analysis, CTSdesign, DFT, design rule and connectivityverification, timing closure.
3. Successfully gone through complete product development cycle. Goodanalytical and debugging skills
4. Good listening, writing and speaking English.
5. Good communication skills, strong interpersonal skills and the flexibility.Dedicated, hard working and good team player
6. Familiar with Back-End (physical design) EDA tools (synopsys,cadence,magma)
7. Familiar with Front-End EDA tools or circuit design is a plus
8. Familiar with Unix/Linux environment and good at scripts
因此，想请教一下各位牛人，在数字后端设计过程中，对DFT需要做哪些必要的处理呢?谢谢各位了。（个人感觉在逻辑综合时，对scan_chain的处理才是真的多。）
1.MSEE with 3+ years or Bachelor with 5+ years of industrial experience in ASICdesign
2. Expertise in place and routing, signal integrity, power analysis, CTSdesign, DFT, design rule and connectivityverification, timing closure.
3. Successfully gone through complete product development cycle. Goodanalytical and debugging skills
4. Good listening, writing and speaking English.
5. Good communication skills, strong interpersonal skills and the flexibility.Dedicated, hard working and good team player
6. Familiar with Back-End (physical design) EDA tools (synopsys,cadence,magma)
7. Familiar with Front-End EDA tools or circuit design is a plus
8. Familiar with Unix/Linux environment and good at scripts
因此，想请教一下各位牛人，在数字后端设计过程中，对DFT需要做哪些必要的处理呢?谢谢各位了。（个人感觉在逻辑综合时，对scan_chain的处理才是真的多。）
scan cts， scan chain reorder，
just so so...
一般没有做怎么处理，在place 阶段 加优化选项就ok了
晕，我们这边dft都是独立的一个组。
首先你得检查网表的drc问题，有drc问题，要让前端人员修改（这是后端对前端的支撑）
其次，你要跟随综合和partition策略，确定dft策略，（后端对patition划分的支持）
详细了解crg设计，支持crg设计满足设计可测试要求。
确定插链的策略，链的条数，长度，跟测试成本强相关，
还有mbist，jtag。
dft模式下的sta。
貌似你们的芯片不小啊。啥公司啊?