setup timing violation

setup timing violationencounter 从 timeDesign -prePlace 开始，setup timing slack 有 -15ns, 一直到　postroute, setup timing violation 修复不了，我对　timing anasysis 不熟悉，请各位帮忙看看那里有问题，该如何解决．谢谢
＊＊＊＊＊＊＊＊＊＊＊＊＊＊＊prePlace.summary
+--------------------+---------+---------+---------+---------+---------+---------+
|Setup mode|all| reg2reg | in2reg| reg2out | in2out| clkgate |
+--------------------+---------+---------+---------+---------+---------+---------+
|WNS (ns):| -15.355 | -1.650| -0.365| -7.044| -6.639| -6.639|
|TNS (ns):|-170.314 | -36.096 | -1.303|-108.463 | -52.836 | -52.836 |
|Violating Paths:|81|50|11|24|8|8|
|All Paths:|11180|11065|379|27|8|76|
+--------------------+---------+---------+---------+---------+---------+---------+
Density: 0.000%
Real DRV (fanout, cap, tran): (0, 2, 0)
Total DRV (fanout, cap, tran): (0, 5, 24)
------------------------------------------------------------
***************************preplace_all.tarpt
*info: Report constrained paths
*Path type: max
*Format: long
*Operating Condition: ss_1v62_125c
*Process: 1.0000
*Voltage: 1.6200
*Temperature: 125.0000
*Time Unit: 1ns
*Capacitance Unit: 1.000000pf
--------------------------------------------------------------------------------------------------------------------------
Path #: 1
Startpoint: sg128_core_i_sg128_handler_i_sg128_handler_mcuif_i_fc_pwrcntl_reg__2__0/Q
(clocked by clk60mhz F)
Endpoint: phy_and_bist_i_usb20phya/SUSPENDM
(clocked by clk_ideal R)
Data required time: 16.000
Data arrival time: 31.355
Slack: -15.355 ( VIOLATION)
Object nameDelta f/r (ns)Sum f/r (ns)Slew (ns)Load (pf)Cell Location (um)
--------------------------------------------------------------------------------------------------------------------------
phy_and_bist_i_usb20phya CKSIE600.000f/-r12.000f/-r0.000f/0.000r0.025(0.00, 291.87)
U193 A->Y (INVX2M)0.000r/-f12.000r/-f0.000r/0.000f0.018(0.00, 0.00)
sg128_chip_globalcntl_i_U92 A->Y (AND2X2M)
0.000r/-f12.000r/-f0.000r/0.000f0.024(0.00, 0.00)
sg128_chip_globalcntl_i_U78 B0->Y (AOI22X1M)
0.000f/-r12.000f/-r0.000f/0.000r0.023(0.00, 0.00)
sg128_chip_globalcntl_i_U32 A->Y (INVX2M)
0.000r/-f12.000r/-f0.000r/0.000f0.024(0.00, 0.00)
sg128_chip_testcntl_i/U51 A0N->Y (OAI2BB1X4M)
0.000r/-f12.000r/-f0.000r/0.000f9.322(0.00, 0.00)
sg128_core_i_sg128_handler_i_sg128_handler_mcuif_i_fc_pwrcntl_reg__2__0 CK->Q (SDFFRQX1M)
0.481r/-f12.481r/-f0.000r/0.000f0.008(0.00, 0.00)
U14979 A->Y (INVXLM)0.082f/-r12.563f/-r0.125f/0.144r0.004(0.00, 0.00)
U16794 A0->Y (AO22XLM)0.293f/-r12.855f/-r0.089f/0.121r0.003(0.00, 0.00)
phy_and_bist_i_usb20phya SUSPENDM (MSU105V13)
0.000f/-r12.855f/-r0.106f/0.109r0.003(0.00, 291.87)
phy_and_bist_i_usb20phya SUSPENDM (MSU105V13) "set_output_delay"
18.500f/-r31.355f/-r
--------------------------------------------------------------------------------------------------------------------------
Path #: 2
Startpoint: sg128_core_i_sg128_handler_i_sg128_handler_mcuif_i_fc_flashif_deative_reg/Q
(clocked by clk60mhz F)
Endpoint: fale
(clocked by clk60mhz F)
Data required time: 27.000 (minus uncertainty: 1.000)
Data arrival time: 34.044
Slack: -7.044 ( VIOLATION)
Object nameDelta f/r (ns)Sum f/r (ns)Slew (ns)Load (pf)Cell Location (um)
--------------------------------------------------------------------------------------------------------------------------
phy_and_bist_i_usb20phya CKSIE600.000f/-r12.000f/-r0.000f/0.000r0.025(0.00, 291.87)
U193 A->Y (INVX2M)0.000r/-f12.000r/-f0.000r/0.000f0.018(0.00, 0.00)
sg128_chip_globalcntl_i_U92 A->Y (AND2X2M)
0.000r/-f12.000r/-f0.000r/0.000f0.024(0.00, 0.00)
sg128_chip_globalcntl_i_U78 B0->Y (AOI22X1M)
0.000f/-r12.000f/-r0.000f/0.000r0.023(0.00, 0.00)
sg128_chip_globalcntl_i_U32 A->Y (INVX2M)
0.000r/-f12.000r/-f0.000r/0.000f0.024(0.00, 0.00)
sg128_chip_testcntl_i/U51 A0N->Y (OAI2BB1X4M)
0.000r/-f12.000r/-f0.000r/0.000f9.322(0.00, 0.00)
sg128_core_i_sg128_handler_i_sg128_handler_mcuif_i_fc_flashif_deative_reg CK->Q (SDFFRHQX8M)
0.273f/-r12.273f/-r0.000f/0.000r0.033(0.00, 0.00)
U231 A->Y (DLY1X1M)0.751f/-r13.024f/-r0.082f/0.112r0.058(0.00, 0.00)
U232 A->Y (CLKINVX8M)0.138r/-f13.162r/-f0.880r/0.758f0.029(0.00, 0.00)
U233 A->Y (BUFX24M)0.158r/-f13.320r/-f0.160r/0.170f0.108(0.00, 0.00)
sg128_core_i_U23 B->Y (NOR2BXLM)0.077f/-r13.397f/-r0.077f/0.102r0.003(0.00, 0.00)
sg128_chip_testcntl_i/U311 A->Y (AND2X2M)
0.200f/-r13.597f/-r0.084f/0.197r0.012(0.00, 0.00)
U442 AN->Y (NOR2BX12M)0.142f/-r13.739f/-r0.104f/0.143r0.003(0.00, 0.00)
U213 A->Y (DLY1X1M)0.845f/-r14.584f/-r0.046f/0.076r0.072(0.00, 0.00)
fale_pad OEN->PAD (PBL8R)11.460f/-r26.044f/-r1.518f/1.764r46.959(1593.69, 652.00)
fale0.000f/-r26.044f/-r21.750f/19.969r 46.959
fale "set_output_delay"8.000f/-r34.044f/-r
--------------------------------------------------------------------------------------------------------------------------
******************************preplace.slk
# Format: clocktimeReqslackR/slackFsetupR/setupFinstName/pinName# cycle(s)
clk60mhz(F)->clk_ideal(R) -2.500*/-15.355*/18.500phy_and_bist_i_usb20phya/SUSPENDM1
clk60mhz(F)->clk60mhz(F) 19.000*/-7.044*/8.000fcle1
clk60mhz(F)->clk60mhz(F) 19.000*/-7.044*/8.000fale1
idealclk_uninand(F)->xfrd_n(F) 26.50012.259/*0.000/*sg128_core_i_sg128_handler_i_sg128_handler_uninand_i_U228/B1
idealclk_uninand(F)->idealclk_uninand(F) 20.000*/-6.639*/4.000xfio41
idealclk_uninand(F)->idealclk_uninand(F) 20.000*/-6.639*/4.000xfio61
idealclk_uninand(F)->idealclk_uninand(F) 20.000*/-6.639*/4.000xfio51
idealclk_uninand(F)->idealclk_uninand(F) 20.000*/-6.639*/4.000xfio31
idealclk_uninand(F)->idealclk_uninand(F) 20.000*/-6.639*/4.000xfio71
idealclk_uninand(F)->idealclk_uninand(F) 20.000*/-6.626*/4.000xfio01
idealclk_uninand(F)->idealclk_uninand(F) 20.000*/-6.538*/4.000xfio11
idealclk_uninand(F)->idealclk_uninand(F) 20.000*/-6.476*/4.000xfio21
clk60mhz(F)->clk60mhz(F) 19.000*/-6.164*/8.000fce1_n1
clk60mhz(F)->clk60mhz(F) 19.000*/-5.472*/8.000fce0_n1
clk60mhz(F)->xfrd_n(F) 26.50014.169/*0.000/*sg128_core_i_U24/B1
clk60mhz(F)->xfrd_n(F) 26.500*/13.652*/0.000sg128_core_i_U75/A11
clk60mhz(F)->xfrd_n(F) 26.500*/13.652*/0.000sg128_core_i_U76/A11
clk60mhz(F)->xfrd_n(F) 26.500*/13.652*/0.000sg128_core_i_U74/A11
clk60mhz(F)->xfrd_n(F) 26.500*/13.652*/0.000sg128_core_i_U77/A11
clk60mhz(F)->xfrd_n(F) 26.500*/13.652*/0.000sg128_core_i_U73/A11
clk60mhz(F)->xfrd_n(F) 26.500*/13.652*/0.000sg128_core_i_U79/A11
clk60mhz(F)->idealclk_uninand(F) 20.000*/-4.891*/4.000xfrb_n1
clk60mhz(F)->xfrd_n(F) 26.500*/13.652*/0.000sg128_core_i_U78/A11
clk60mhz(F)->xfrd_n(F) 26.500*/13.652*/0.000sg128_core_i_U80/A11
clk60mhz(F)->xfrd_n(R) 18.500*/6.072*/0.000sg128_core_i_U14/B1
clk60mhz(F)->xfrd_n(F) 26.500*/13.929*/0.000sg128_core_i_U79/A01
clk60mhz(F)->xfrd_n(F) 26.500*/13.937*/0.000sg128_core_i_U74/A01
clk60mhz(F)->xfrd_n(F) 26.500*/13.937*/0.000sg128_core_i_U75/A01
clk60mhz(F)->xfrd_n(F) 26.500*/13.955*/0.000sg128_core_i_U73/A01
clk60mhz(F)->xfrd_n(F) 26.500*/13.955*/0.000sg128_core_i_U77/A01
clk60mhz(F)->xfrd_n(F) 26.500*/13.961*/0.000sg128_core_i_U76/A01

看上去很高深

学习学习！

the description“phy_and_bist_i_usb20phya CKSIE60”in path 1 relates to an original delay " 12.000f/-r " and an output delay "18.500f/-r", the sum of them is 30.500ns.but the required time is "16.000ns" which means that even path 1 is 0 delay , the slack is -14.500ns.
change your constraints and setreasonable values for the input delays and output delays and you will resolve this problem.

7#说得对。明显约束不合理。怎么可能修复得了

Startpoint: sg128_core_i_sg128_handler_i_sg128_handler_mcuif_i_fc_pwrcntl_reg__2__0/Q
(clocked by clk60mhz F)
Endpoint: phy_and_bist_i_usb20phya/SUSPENDM
(clocked by clk_ideal R)
这两个是同一个clock?如果不是有可能是false path，design里面要保证不会有synchronization的问题

constraint shall be optimized

我也有过这样的violation，然后我就将对应的INPUT端口的set_drive设置的大一点儿，或者将OUTPUT端口的set_load设置的小一点，然后就没有violation了，不知道这样对不?大家给个建议。谢谢。

好像没讲清啊。