icc bus names change

Hi, all,
plz help me with the following issues, thanks.
supposing I have a 8bit bus output pin in my layout in ICC flow, bus[0]~bus[7], why names of some wires are changed unexpected, eg, the wire connected to bus[5] pin are changed to "n48", and as a result, when back-annotating the spef during signoff STA, PT issues the following errors:
../logs/design.TYP.starrc_typ_25.log:Error: Cannot find port/pin 'n48' in design 'design' (DES-002)
../logs/design.TYP.starrc_typ_25.log:Error: Invalid capacitor (n48 0.007514) on net u_design/u_sub1/u_sub2/bus[5]:
and now I fixed this by changing the name of that wire from 'n48' to bus[5] in ICC manually, and no errors will be issued during STA,
and I wonder why the names are changed unexpectedly? and the method above is proper or not? or should I check anything else for any potential problems,
thanks in advance.
regards,
henry

for unique and complete database ,spef and verilog should match ,
for some habit or verilog name correctness ,will use
change_names -rules verilog -hierbefore dump verilog ,
the same asDC ,then save_mw_cel ,do spef extraction ,

Star-RC做寄生参数文件的话，可能是没有抽完整，you can find those nets name and it‘s RC value whether exist or not, also you can check you netlist or .cdl