ICC setup violation

Hi, all
plz help me with the following issue, thanks in advance.
when implementing the layout, no setup-violation is issued during setup & floorplan, however, when placement is done, things goes
differently:
and here is the timing report:
****************************************
Report : timing -path full_clock_expanded -delay max -slack_lesser_than -5.00 -max_paths 1 -transition_time
Design : design
Scenario(s): func_osc_48M
Version: E-2010.12-ICC-SP3-1
Date: Sat Nov 26 19:11:15 2011
****************************************
Startpoint: u_design_core/u_sub1/sub2_r_o_reg
(rising edge-triggered flip-flop clocked by designter_clk_dec)
Endpoint: R_O_PAD (output port clocked by designter_clk_dec)
Scenario: func_osc_48M
Path Group: designter_clk_dec
Path Type: max
PointTransIncrPathVoltage
------------------------------------------------------------------------------------
clock designter_clk_dec (rise edge)0.000.00
clock network delay (ideal)3.003.00
u_design_core/u_sub1/sub2_r_o_reg/CK (SDFPSBNRQ1)
1.000.00 #3.00 r4.50
u_design_core/u_sub1/sub2_r_o_reg/Q (SDFPSBNRQ1)
43.7420.3623.36 f4.50
u_design_core/u_sub1/sub2_r_o (sub1)0.0023.36 f4.50
u_design_core/r_o (design_core)0.0023.36 f4.50
u_io_pad/r_o_cc (io_pad)0.0023.36 f4.50
u_io_pad/r_o/PAD (POT24)4.609.69 *33.04 f4.50
u_io_pad/r_o_pad (io_pad)0.0033.04 f4.50
R_O_PAD (out)4.600.00 *33.04 f4.50
data arrival time33.04
clock designter_clk_dec (rise edge)20.0020.00
clock network delay (ideal)3.0023.00
clock uncertainty-3.1019.90
output external delay-8.0011.90
data required time11.90
------------------------------------------------------------------------------------
data required time11.90
data arrival time-33.04
------------------------------------------------------------------------------------
slack (VIOLATED)-21.14
and from above CLK to Q is more than 20ns, becaused of the unexpected transition time, and now I have two questions:
1.u_design_core/u_sub1/sub2_r_o_reg/CK (SDFPSBNRQ1)
1.000.00 #3.00 r4.50
u_design_core/u_sub1/sub2_r_o_reg/Q (SDFPSBNRQ1)
43.7420.3623.36 f4.50
what's the transition time above, eg, the 43.74 means the transition time of the pin "sub2_r_o_reg/D"(data input port)? why is it so big?
2.why does this happen and how to fix this issue?
regards,
henry

sincerely hoping for your help, thanks
sos

too big transition harm this timing,
which process ?
43.7 is the transition of SDFPSBNRQ1/Qpin,please report_timing -cap -input_pins-trans -nets
to see the details
i think there must be huge load after Q pin ,which degrade this flop's timing ,