VHDL attribute 问题

attribute DLL_FREQUENCY_MODE: string;
attribute DLL_FREQUENCY_MODEof LclkDcm : label is "HIGH";
-- attribute DLL_FREQUENCY_MODEof SysDcm : label is "LOW" ;
attribute CLKOUT_PHASE_SHIFT: string;
attribute CLKOUT_PHASE_SHIFTof LclkDcm : label is "VARIABLE";
-- attribute CLKOUT_PHASE_SHIFTof LclkDcm : label is "FIXED";
-- attribute CLKOUT_PHASE_SHIFTof LclkDcm : label is "NONE";
attribute PHASE_SHIFT: string;
attribute PHASE_SHIFTof LclkDcm : label is "-255";
-- attribute PHASE_SHIFTof LclkDcm : label is "0";
attribute CLKDV_divIDE: string;
attribute CLKDV_divIDEof LclkDcm : label is "3";
-- attribute CLKDV_divIDEof SysDcm : label is "3" ;
attribute DUTY_CYCLE_CORRECTION : string;
attribute DUTY_CYCLE_CORRECTION of LclkDcm : label is "TRUE";
-- attribute DUTY_CYCLE_CORRECTION of SysDcm : label is "TRUE" ;
attribute DESKEW_ADJUST: string;
attribute DESKEW_ADJUSTof LclkDcm : label is "SOURCE_SYNCHRONOUS";
-- attribute DESKEW_ADJUSTof SysDcm : label is "2" ;
attribute CLKIN_divIDE_BY_2: string;
attribute CLKIN_divIDE_BY_2of LclkDcm : label is "FALSE";
attribute RLOC_ORIGIN : string;

如果需把VHDL代码转换成verilog代码，VHDL属性 怎么解决呀。请教。

问下前端版面，