关于PT做POST LAYOUT STA的问题

PT 做POST STA,PT的约束脚本和PRE STA唯一的区别在于去掉了uncertainty,latency,transition 等CLK相关及wire load mode ,operation condition的设置,取而代之的是set_propagated_clock 和read SDF文件.
结果现在问题是芯片内部的TIMING 都没有问题,问题处在IO上.
举来说对于端口dsutx_p约束脚本里面有:
set_output_delay-max xx-clock [get_clock pll_fout1] [get_ports dsutx_p]
上述对与PRE/POST STA都是相同的,但是做POST STA时候就出现了下面的问题:
Startpoint: topcore/sparc0/dcom0/dcom_uart0/r_reg_TSHIFT__0_
(rising edge-triggered flip-flop clocked by pll_fout1)
Endpoint: dsutx_p (output port clocked by pll_fout1)
Path Group: pll_fout1
Path Type: max
PointIncrPath
------------------------------------------------------------------------------
clock pll_fout1 (rise edge)0.000.00
clock network delay (propagated)3.12 *3.12
topcore/sparc0/dcom0/dcom_uart0/r_reg_TSHIFT__0_/CK (DFFRHQX1)
0.003.12 r
topcore/sparc0/dcom0/dcom_uart0/r_reg_TSHIFT__0_/Q (DFFRHQX1)
0.54 *3.67 r
topcore/sparc0/dcom0/dcom_uart0/BL1_R_BUF_60/Y (BUFX12)
0.21 *3.87 r
BW1_BUF97168/Y (BUFX16)0.20 *4.07 r
pad178/PAD (PDO08CDG)2.93 *7.00 r
dsutx_p (out)0.00 *7.00 r
data arrival time7.00
clock pll_fout1 (rise edge)10.0010.00
clock network delay (propagated)0.0010.00
output external delay-5.005.00
data required time5.00
------------------------------------------------------------------------------
data required time5.00
data arrival time-7.00
------------------------------------------------------------------------------
slack (VIOLATED)-2.00
以上报表我们可以看出对于start point 和end point 的clock network delay,
在PRE STA的时候是clock network delay(ideal)4
而POST STA的时候是start point---> clock network delay (propagated)3.12 *3.12
end point---->clock network delay (propagated)0.0010.00
差别在于end point时候POST STA 的时钟延时为0 ,从而造成了TIMING VIOLATION.
这种现象的原因是怎么造成的?请给分析一下
谢谢！

有些奇怪，clock path没有把latency算上，可以update_timing看看，如果不行，可能是工具版本bug吧。