Cadence上海office职位

现在公司招人， 如有兴趣 请把简历发到我的公司邮箱：
cjchen@cadence.com

内部推荐， 成功几率高。
公司介绍： cadence, 美资EDA软件公司。 详情请google或者baidu
公司地址： 地铁7号线花木路站 浦东嘉里城。
R&D
1. Senior Software Engineer for EDI IPO (Req#: 7038)
Hiring Manager: Yuhua Yang
Position Description:
 Working on EDI IPO function on CCR fixing, memory and performance profiling as well as new enhancements.
Position Requirements:
 MS/PHD from computer science, EE, math or related
 The candidate must be also smart to capture new EDA technologies, and switch among different areas successfully.
 Strong problem-solving, architecture, algorithmic.
 Familiar with interpreted language such as TCL is a plus.
2. Senior Engineer for flipchip route (Req#: 7039)
Hiring Manager: Ting Li
Position Description:
 This position is for a R&D engineer to assist in development of detailed route in flipchip design.
 The candidate will be responsible for designing, developing, troubleshooting and debugging software programs of routing flow and related algorithms.
Position Requirements:
 The candidates should have strong software programming skill with C/C++ on Linux/Unix platform.
 Strong desires to learn and explore new technologies and is able to demonstrate good analysis and problem solving skills
 EDA software development experience or IC design knowledge, especially in backend and flipchip design.
 Know basic routing algorithms.
 Good English communication skill, both oral and written.
3. Senior Member of Technical Staff (Req#: 7548)
Hiring Manager: Jeffery Zhang
Position Description:
 Responsible for developing and maintain physical verification engine in EDI systems.
 Responsible for implementation for physical design rule check of advanced node process.
 Responsible for performance improvement in current physical verification engine.
Position Requirements:
 The candidate should be very strong at complex software development with C or C++ on UNIX platform, domain knowledge at Physical Design Rule is preferred.
 The candidate will be responsible for development of complicated algorithms to check design rule violation among huge geometries, the experience to handle large data manipulation is preferred.
 The candidate should have 3 years software development experience with MS or PHD degree of CS/EE/Math or others related.
 Good team player with strong written and verbal communication skills
 Familiar with LEF/DEF is preferred, and the ability to geometrical operation is definitely a plus.
4. Senior Member of Consulting Staff (计算电磁学算法工程师) (Req# 7618)
Hiring Manager: Jingping Zhang
Position Description:
 Be responsible for designing, developing, and maintaining software products in the field of Signal Integrity, Power Integrity, and Electromagnetic Field and Circuit Simulation.
 Research and development of new algorithms.
 Design and develop new features and improve engine capabilities with efficient prototyping, code implementation, unit test and verification.
 Contribute new ideas/solutions to resolve challenging technical issues.
 Optimize the existing software architecture and code data structure.
 Quickly identify software/algorithm problems in the support cases.
 Good communication skill is required as the position will work with teams at diversified locations worldwide.
Position Requirements:
 CS/EE/Math MS degree with 5+ years or Ph.D. degree with EDA experience.
 Knowledge of circuit analysis principles.
 Knowledge of computational electromagnetic.
 Strong C/C++ programming skill.
 Electromagnetic software tool development & usage.
 Good communication skill and proficiency in English (written and oral).
 Strong C/C++ programming capability and EM field or circuit simulation background.
 The position opened this time also prefers Ph.D., and any experience on PCB/Package modeling is a plus.
5. Member of Technical Staff Hardware (Req#: 7640)
Hiring manager: Marco Zavaroni
Position Description:
 Responsible for designing and developing sub-systems and modules or components of hardware based verification products. In addition modifying, updating and productizing existing hardware based verification products. Perform as individual contributor on FPGA based design projects involving board design, RTL design, verification, productizing and documentation. Work on diverse problems related to FPGA design, simulation or verification issues.
Position Requirements:
 The position requires BSEE, or equivalent
 Must have excellent communication skills, both written and verbal.
 Technical expertise in FPGA design for either Altera or Xilinx products is required.
 Experience in FPGA design methodologies including high speed design, serial protocols and FPGA timing closure is desired.
 In addition RTL design knowledge using Verilog is required along with experience in using RTL verification tools and flows.
 Verification using Cadence simulation products is desired.
 Experience with scripting languages like Perl, TCL C-shell is strongly recommended.
 Experience with PCB tools is also desired. Experience with high speed memory interface design is also desired.

PV
1. Lead PV Design Engineer (Req#: 7493)
Hiring Manager: Hong Yin
Position Description:
 Work through synthesis flow and APR flow by solving different kind of issues and bottleneck, througn many designs.
 Identify any timing/power/area issues within SYN/APR flow, and among flow interfaces.
 Develop system for automation.
Position Requirements:
 MS with 3 years work experience in design house or EDA company.
 Good at STA, good at APR flow, including place, route, cts, optimization, and SI analysis
 Know about RTL synthesis.
 Good at unix scripts, cshell. Perl is a plus.
 Strong ability in analysis and solving issues, strong ability in facing difficulty and challenges. Proactive in work.
 Good English skill, communication skill and good team work.
2. PVS Lead Engineer (Req#: 7580)
Hiring Manager: Hua Ding
Position Description:
 As PV engineer, s/he will be responsible for product validation for PVS and flow validation for Virtuoso/Encounter flows.
 The candidate will develop & execute the test plans, develop & automate test cases and maintain regression suite for stability and quality.
 The candidate needs to be able to debug test failures, assess problem impact and report test failures and evaluate root cause for product improvement.
 This person should have effective communication skills in English, both written and verbal. S/he should also have proactive personality and skill set to work within the PV group and cross functional groups, such as R&D, PE and Marketing.
Position Requirements:
 Must have 5+ years of experience with physical verification tools (Calibre/ICV DRC, LVS and RCX) as a Quality Engineer or Applications Engineer.
 Must have SOLID WORKING EXPERIENCE with UNIX and scripting - shell, Perl, Knowledge of QA practices, methodologies, and procedures Experience with physical verification tools.
 Preferred - MSEE/CS, Minimum - BSEE/CS
 Preferred - 6+ years, Minimum - 3 years with Physical verification tools, such as Calibre or ICV in DRC, LVS and/or RCX area.
3. Lead PV Engineer-DFM (Req# 7735)
Hiring Manager: Hua Ding
Position Description:
 Responsible for developing and implementing test methodologies, analyzing test data and maintaining regression.
 Develop the automatic test system for Cadence products
 Work closely with a group of professionals in R&D, PE, and Software Release team to enhance the quality of MVS products
Position Requirements:
 MS or above majored in EE or CS.
 Good experience in IC design flow on Virtuoso or Encounter platform.
 Familiar with DRC, LVS and QRC, Customer layout and tape out experiences is preferable
 Shell/Perl programming skill.
 Candidate must have excellent ability to learn, explore and solve problems, have team-cooperating and innovating spirit,
 Candidate must possess good Chinese and English communication skills;

PE
1. Principal Product Engineer for Digital Back-end Reference Flow (Req#: 7156)
Hiring Manager: Xiaoli Chen
Position Description:
 Responsible for RTL-to-GDSII digital reference flow development and optimization, for designs from 500MHz to GHz at advance process nodes, for key customer foundries in Asia.
 Provide technical consultant about library qualifications for key customer foundries in Asia.
 Play a leading role among other team members, while receive little instruction on routine and general assignments.
Position Requirements:
 Bachelor's degree with 8+ years experience or master’s degree with 6+ year’s experiences in IC design.
 Strong ability and hands-on experiences in RTL-to-GDSII design flow and methodology, for designs from 500MHz to several GHz big chips.
 Have real design experience including logic synthesis, P&R, CTS, STA and SSTA, MMMC to close timing, power and die area.
 Working experience in multi-nation IC design house is preferred.
 Good communication in English and Chinese, team-spirit, self-motivated.
2. Senior Product Engineer for QRC (Req#: 7561)
Hiring Manager: Xiaoli Chen
Position Description:
 Focus on QRC advanced solutions.
 Responsible for integrating Cadence QRC into Cadence reference flows, for high-speed and advanced node designs (20nm/16nm).
 Work on parasitic RC correlation and timing correlation between digital implementation tool and signoff tool, for better QoR.
 Work on PVS-QRC solutions in both digital and analog design flows.
 Provide in-depth technical consultant to foundry customers about Cadence digital signoff solutions, and usage of Cadence QRC in digital implementation and signoff cycles.
Position Requirements:
 Bachelor's degree with 5+ years experience or master’s degree with 2.5+ year’s experiences in IC design.
 In-depth knowledge in parasitic RC extraction methodology, accuracy analysis and correlation, and so on.
 In-depth expertise in extraction tools among various scales of designs, especially at advanced nodes.
 Hands-on experiences in RTL-to-GDSII design projects, for designs from 500MHz to several GHz big chips.
 Working experience in multi-nation IC design house is preferred.
 Good communication in English and Chinese, team-spirit, self-motivated.
3. Senior Product Engineer - PVS (Req#: 7561)
Hiring Manager: Xiaoli Chen
Position Description:
 Focus on PVS physical verification solutions.
 Responsible for integrating Cadence PVS into Cadence reference flows, for high-speed and advanced node designs (20nm/16nm).
 Work on DRC correlation between digital implementation tool and PVS, to achieve better QoR in digital implementation.
 Work on physical verification solutions, including DRC and LVS for various designs from block level full-chip designs of million gates.
 Provide technical consultant to foundry customers about Cadence PVS relevant solutions in design implementation and signoff cycles.
Position Requirements:
 Bachelor's degree with 5+ years experience or master’s degree with 2.5+ year’s experiences in IC design.
 In-depth expertise in physical verification among various scales of designs including both analog and digital.
 In-depth knowledge of DRC and LVS methodology.
 Working experience in multi-nation IC design house is preferred.
 Good communication in English and Chinese, team-spirit, self-motivated.
4. Senior Product Engineer for DFM (Req#: 6958)
Hiring Manager: Hua Ding
Position Description:
 Responsible for promoting DFM solutions on Advanced node.
 Engage with sales team to identify and scope opportunities for DFM products
 Work closely with R&D team to deploy solution to customers
 Work with customers to build & validate DFM model, setup the application flow, resolve technical issues and get feedback from customers to drive the development and enhancement of DFM products
 Interface with cross-function team to create technical solutions
Position Requirements:
 Master with 3+ years’ working experience or Bachelor with 5+ years’ experience in IC design
 Be familiar with digital back-end design flow
 Experiences with Cadence Virtuoso and Encounter
 Experiences with OPC/DFM is a plus
 Good communication in English and Chinese, good confidence and good self-motivation.
5. Senior/PVS Product Engineer
Hiring Manager: Runze Li
Position Description:
 The Product Engineering team works with Customers and foundries, R&D, Marketing, and the Field Applications Engineers to create products that address the unique and complex needs of our customers. A Physical Verification Product Engineer provides in-depth technical expertise in writing Physical Verification rule decks (i.e. DRC, ERC, FILL and LVS) and the usage of Physical Verification tools throughout physical implementation and signoff verification cycles.
Responsibilities:
 Develop Physical Verification rule decks (i.e. DRC, ERC, FILL and LVS)
 Setup efficient flows to improve rule deck development quality and product performance.
 Run expert-level benchmarks and solve complex customer problems.
 Work with the RD, field, customers and foundries to identify and define product requirement and enhancement
Position Requirements:
 Knowledge of developing rule decks for commercial physical verification tools (e.g. PVS, Calibre, Hercules, Dracula, Assura, etc.) is required.
 Experience in the following areas:
 DRC, includes density, antenna, etc.
 LVS, includes device extraction, parameter measurement, connect/stamp sequences, short isolation, etc.
 Knowledge of netlist formats SPICE, CDL, Verilog, etc.
 DFM, includes yield analysis, via insertion, OPC, FILL, etc.
 Experience with layout implementation tools (e.g. Virtuoso, DesignREV, ICStation, etc.) for the creation of qualification cells is required.
 Knowledge of automating test suites for the qualification of rule decks is a plus.
 Programming of Tcl, Perl, and Skill are a plus
 EDUCATION: BS or MS in Electrical Engineering.


AE
1. Lead Application Engineer (Location: SH) (Req #:7356)
Hiring manager: David Zhang
Position Description:
 Work closely with the Sales team to identify and scope opportunities for Cadence Emulation and Acceleration products.
 Plan, execute and manage key technical evaluations and benchmark with existing and potential customers.
 Train, ramp-up and accompany customer project.
 Conduct basic and advanced trainings, presentations and demos as necessary.
 Providing technical expertise to address clients’ queries, which need expert involvement.
 Aligned closely with corporate engineering and sales/marketing team on customer requirement for product direction/improvement.
Position Requirements:
 4~6 years experience in the following areas:
 HW verification with knowledge of System Verilog/VHDL and HDL simulators
 FPGA prototyping project experience is a must
 Experience with hardware emulator or accelerator is a big advantage
 Advanced Verification Methodology like OVM or VMM is a plus
 Knowledge of UNIX and Linux is highly desired
 Strong verbal and written communication skills in English
 Strong teamwork skills with good human relationship
2. Principle Solution Engineer – Verification (Location: SH) (Req #:7078)
Hiring manager: Riccardo Lavorerio
Position Description:
 The Incisive Solution Engineer works with key customers to understand their design and verification challenges,
 Collaborate with the R&D and PV organization to ensure that the product implementation addresses the customers’ real needs.
 The Solution Engineer plays a pivotal role in defining and deploying Cadence’s Incisive Simulator products
 and solutions at key customers to enables them to do functional verification at a very high performance & efficiency.
 This position requires problem discovery and analysis at customer site, assessment of possible solutions,
 Collaborating with R&D and customer to develop and test the solution, and manage the deployment at the customer site.

 The position also requires mentoring junior application engineers on verification solutions and tool usage.
 The position requires 100% presence in Asia Pacific area.
Position Requirements:
 The candidate should possess minimum a Bachelors technical degree and 5-8 years of industry experience
- Minimum 5 years hands-on, expertise on simulation based design & verification techniques.
- Hands on experience using HDL simulator is a must
- Knowledge on competitor verification flow and tools is a plus
- Hands on Verification experience using SystemVerilog/e/SystemC/Vera
- Hands on Design experience using Verilog, VHDL, SystemC
- Hands-on experience optimizing RTL and Gate-level simulation to improve performance is a
- plus
- Ability to partner with key customers and provide expert support to field application engineers
 The candidate must be able to drive R&D and Application engineers and have passion to make customers successful
- Must be willing to travel worldwide in order to work closely with customers in any part of the world
- Highly organized individual with demonstrated ability to handle multi-task activities and projects
- Passionate about adopting and promoting new technologies and making customers successful
- Building and delivering training content to roll out new solution and methodologies
- Very good communication skills
- English fluency is a must, Chinese and/or Korean speaking language is a plus
- Multi-years working experience with western companies (EMEA or USA) is a plus
- Experience to lead projects and people will be strongly taken into consideration
3. Principle Product Engineer (Location: SH) (Req #:7488)
Hiring manager: Olivier Arnaud
Position Description:
 The Incisive Solution Engineer works with key customers to understand their design and verification challenges,
 Focus on customers applying Cadence Virtuoso Layout tools technologies
 Work with R&D to develop and validate state of the art layout, routing and custom design
 Provide technical feedback to R&D and Marketing to improve product capabilities, effectiveness and performance of solutions through all Cadence Custom IC tools. Work with engineering to identify fixes and workarounds for customer issues
Position Requirements:
 The candidate should possess minimum a Bachelors technical degree and 5-8 years of industry experience
 Experience in custom layout design or EDA industry experience. Expertise using Cadence Virtuoso layout tools or similar; programming proficiency in SKILL or similar language, tcl and Unix/Linux shell scripting; strong communication and teamwork skills
 Preferred: MSEE with around 8 years experience including advanced node designs with 65nm or smaller process rules. Previous experience of custom IC contract, simulation and physical verification a plus. Previous field application, consulting or customer facing experience also plus with key customers and provide expert support to field application engineers

没人有兴趣吗?

我倒是有个朋友相找AE的工作

有兴趣。模拟版图想转这行行不?

能转行不

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感觉CADENCE 每年都在招人

Gives in-depth idea of prerequisites for job