数字前端设计和验证工程师
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公司：北京比特大陆科技有限公司
项目方向：人工智能终端/云端SOC
联系方式：peng.gao@bitmain.com
13810106528
欢迎邮件和微信咨询
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BITMAIN致力于解决世界上最具挑战性的人工智能计算问题。无论你是在寻求实习机会，还是工作机会，我们都为那些有抱负以改善世界，并且享受科技的人们提供非同一般的岗位。
BITMAIN的员工非常多样化，是由一群专注、创新、有才能的专业人士组成的团队。在Sophon工作意味着你与一个全球领先的技术专家建立了联系。你可以与不同学科领域的杰出人士分享你的见解，提高你的技能。
BITMAIN提供有竞争力的薪水、综合福利和一系列额外津贴。我们的办公环境休闲舒适，配有健身设施，阅读室及休闲中心。我们倡导弹性的工作时间，高效率的团队协作。每年一次提供免费体检，集体出游。定期举办员工生日会和下午茶歇。我们的目标是希望吸引和留住世界上最优秀的人才。
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资深/高级芯片设计工程师
工作地点：北京、上海 工作经验：5或3年 教育经历：硕士 工作性质：全职
职位描述
1. Participate in RISCV or Deep Learning Accelerator or other SOC IP design for all frontend phase
2. Specification define
3. RTL implementation
4. Analysis and optimization for performance
5. Analysis and optimization for power
6. Analysis and optimization for timing
7. Design flow: lint/synthesis/sta/formal check
8. Silicon debugging
职位要求
1. MS with 5+ or 3+ years of experience in ASIC design
2. Experience with USB/MIPI_CSI/MIPI_DSI or other high speed interface IPs design are highly desirable
3. Experience with RISC CPU (RISCV/MIPS/ARM) related IPs design are highly desirable
4. Experience with Deep Learning Accelerator related IPs design are highly desirable
5. Experience with all phases of frontend architecture, design and validation
6. RTL Coding, design reviews, SYN, CDC, FEV
7. Demonstrated work experience with timing analysis, area and power optimizations, performance analysis, debug ability, ECOs, and post-silicon debug
8. Excellent knowledge of Verilog and popular EDA simulation & implementation tools
9. Good experience in scripting languages like Perl, Unix shell or similar languages
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资深/高级芯片验证工程师
提交简历
工作地点：北京、上海 工作经验：5或3年 教育经历：硕士 工作性质：全职
职位描述
1. Develop test plans, tests and verification infrastructure for complex IP's/sub-system/SOC's
2. Create verification environment for both directed and random verification
3. Create reusable bus functional models, monitors, checkers and scoreboards
4. Drive functional coverage driven verification closure
5. Work with architects, designers and post-silicon teams
职位要求
1. MS with 5+ or 3+ years of experience in design verification
2. Experience with USB/MIPI_CSI/MIPI_DSI or other high speed interface IPs verification are highly desirable
3. Experience with RISC CPU (RISCV/MIPS/ARM) related IPs verification are highly desirable
4. Experience with Deep Learning Accelerator related IPs verification are highly desirable
5. Excellent knowledge of popular EDA simulation tools (VCS or equivalent simulation tools, debug tools like Debussy, Simvision)
6. Experience in System Verilog or similar HVL is highly desirable
7. C++ programming language experience desirable
8. Scripting knowledge (Perl/shell)
9. Excellent communication skills and ability to lead highly competent team.
项目方向：人工智能终端/云端SOC
联系方式：peng.gao@bitmain.com
13810106528
欢迎邮件和微信咨询
============================================================================================
BITMAIN致力于解决世界上最具挑战性的人工智能计算问题。无论你是在寻求实习机会，还是工作机会，我们都为那些有抱负以改善世界，并且享受科技的人们提供非同一般的岗位。
BITMAIN的员工非常多样化，是由一群专注、创新、有才能的专业人士组成的团队。在Sophon工作意味着你与一个全球领先的技术专家建立了联系。你可以与不同学科领域的杰出人士分享你的见解，提高你的技能。
BITMAIN提供有竞争力的薪水、综合福利和一系列额外津贴。我们的办公环境休闲舒适，配有健身设施，阅读室及休闲中心。我们倡导弹性的工作时间，高效率的团队协作。每年一次提供免费体检，集体出游。定期举办员工生日会和下午茶歇。我们的目标是希望吸引和留住世界上最优秀的人才。
============================================================================================
资深/高级芯片设计工程师
工作地点：北京、上海 工作经验：5或3年 教育经历：硕士 工作性质：全职
职位描述
1. Participate in RISCV or Deep Learning Accelerator or other SOC IP design for all frontend phase
2. Specification define
3. RTL implementation
4. Analysis and optimization for performance
5. Analysis and optimization for power
6. Analysis and optimization for timing
7. Design flow: lint/synthesis/sta/formal check
8. Silicon debugging
职位要求
1. MS with 5+ or 3+ years of experience in ASIC design
2. Experience with USB/MIPI_CSI/MIPI_DSI or other high speed interface IPs design are highly desirable
3. Experience with RISC CPU (RISCV/MIPS/ARM) related IPs design are highly desirable
4. Experience with Deep Learning Accelerator related IPs design are highly desirable
5. Experience with all phases of frontend architecture, design and validation
6. RTL Coding, design reviews, SYN, CDC, FEV
7. Demonstrated work experience with timing analysis, area and power optimizations, performance analysis, debug ability, ECOs, and post-silicon debug
8. Excellent knowledge of Verilog and popular EDA simulation & implementation tools
9. Good experience in scripting languages like Perl, Unix shell or similar languages
=========================================================================================
资深/高级芯片验证工程师
提交简历
工作地点：北京、上海 工作经验：5或3年 教育经历：硕士 工作性质：全职
职位描述
1. Develop test plans, tests and verification infrastructure for complex IP's/sub-system/SOC's
2. Create verification environment for both directed and random verification
3. Create reusable bus functional models, monitors, checkers and scoreboards
4. Drive functional coverage driven verification closure
5. Work with architects, designers and post-silicon teams
职位要求
1. MS with 5+ or 3+ years of experience in design verification
2. Experience with USB/MIPI_CSI/MIPI_DSI or other high speed interface IPs verification are highly desirable
3. Experience with RISC CPU (RISCV/MIPS/ARM) related IPs verification are highly desirable
4. Experience with Deep Learning Accelerator related IPs verification are highly desirable
5. Excellent knowledge of popular EDA simulation tools (VCS or equivalent simulation tools, debug tools like Debussy, Simvision)
6. Experience in System Verilog or similar HVL is highly desirable
7. C++ programming language experience desirable
8. Scripting knowledge (Perl/shell)
9. Excellent communication skills and ability to lead highly competent team.