北京数字类岗位- 西二旗,知春路,奥北科技园,北三环双安
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北京数字岗位整理,有兴趣的可以发简历到hamy@hibohr.com,或者加微信13512136297 及时沟通,谢谢
北京西二旗 地铁站附近 SOC设计工程师岗位
芯片设计工程师—北京 4HC
职位描述:
1. ARM SOC 架构设计
2. ARM SOC 顶层集成
2. ARM SOC 的模块设计
任职要求:
Must have:
1. 精通 Verilog 语言
2. 了解UVM方法学;
3. 3-4年芯片设计经验;
4. 1个以上的SOC 项目设计经验
5. 精通AMBA协议
6. 良好的沟通能力和团队合作能力
Preferred to have:
1. ARM 子系统设计经验
2. AMBA 总线互联设计
3. DDR3/4, SD/SDIO设计经验
4. UART/SPI/IIC 设计调试经验
4. 芯片集成经验
北京 海淀区知春路 数字设计 ,数字验证工程师
ASIC数字电路设计验证工程师 (数字设计 或者数字验证都需要)
岗位职责:
1、根据系统组的需求,整理需求文档;
2、完成模块的设计文档;
3、完成模块的设计;
4、
完成模块的单元验证,给出测试报告/覆盖率分析报告;
5、协助系统验证工程师/FPGA测试工程师定位/解决问题。
任职要求:
1、微电子,计算机或者通信相关专业;
2、熟悉数字逻辑设计,掌握Verilog HDL,有相关软件实习应用经验;
3、熟悉验证,熟悉SystemVerilog;
4、了解综合/DFT/STA;
5、熟悉SoC架构、ARM体系、AMBA总线;
6、熟悉Synopsys开发工具;
7、掌握脚本语言如bash/perl,掌握Makefile;
8、良好的沟通能力和文档写作功底。
加分项:
1、熟悉VMM/OVM/UVM加分;
2、有通信背景加分;
3、有成功流片经历加分。
北京奥北科技园附近 8号线林萃桥
资深芯片设计工程师 Senior IC/ASIC/SOC Design Expert
Responsibilities:
IC Block design for all frontend phase
IC chip level design for all font-end phase
Architecture define
RTL implementation
Analysis and Optimization for performance
Analysis and Optimization for power
Analysis and Optimization for timing
Design flow: lint/synthesis/sta/formal check
Silicon debugging
Requirements:
BS / MS with 5+ years of experience in ASIC or FPGA design
Experience with CPU related IPs design are highly desirable
Experience as design lead for complex or high speed IPs
Experience with all phases of frontend architecture, design and validation
RTL Coding, Design Reviews, SYN, CDC, FEV, DFT insertion, ATPG analysis
Demonstrated work experience with timing Analysis, Area and Power optimizations, Performance Analysis, Debug ability and Security analysis, ECOs, and Post-Silicon Debug
Excellent knowledge of Verilog and popular EDA simulation & implementation tools
Good experience in scripting languages like Perl, Unix shell or similar languages
北京 双安商场附近
数字集成电路设计
岗位职责:
1. 设计验证数字接口模块
2. 设计验证DSP模块
3. IP集成,SOC设计
4. 设计验证时钟系统和控制系统
职位要求:
1. 熟练使用Verilog/VHDL做逻辑设计,有模块级原生设计能力
2. 熟悉DSP或者高速数字接口
3. 熟悉多时钟域和多电源域设计
4. 能描述模块SDC约束,熟悉数字前端流程,清晰理解概念
5. 有学习能力,能自我驱动,能良好沟通合作
数字前端实现工程师 (工作地点:北京/上海)
Responsibilities
1. Develop timing constraint and low power design constraint
2. Logic synthesis, STA, formal verification, low power check and DFT
3. Co-work with physical design team for timing closure
4. Improve digital front-end flow quality and efficiency
Qualifications
1. 3+ years’ experience
2. Experience with at least three successful chip tapeout
3. Proficient with synthesis, STA, formal verification, low power, DFT
4. Proficient with Design compiler, Prime time and Conformal LEC
5. Proficient with common Linux utility such as Shell, Perl
6. Good knowledge of digital logic design is a plus
7. Good knowledge of physical design is a plus
8. Good team player
数字验证实现工程师 (工作地点:北京/上海)
Responsibilities
1. Maintain/develop verification platform
2. Verification of chip level design
3. Provide verification support to design team
4. Improve verification quality and efficiency
Qualifications
1. 3+ years’ experience
2. Experience with at least one complete and successful chip verification
3. Proficient with Verilog, SystemVerilog and UVM/VMM
4. Proficient with C and script languages (Perl/Shell/Makefile/…)
5. Expert of EDA verification tools
6. Expert of verification methodologies
北京西二旗 地铁站附近 SOC设计工程师岗位
芯片设计工程师—北京 4HC
职位描述:
1. ARM SOC 架构设计
2. ARM SOC 顶层集成
2. ARM SOC 的模块设计
任职要求:
Must have:
1. 精通 Verilog 语言
2. 了解UVM方法学;
3. 3-4年芯片设计经验;
4. 1个以上的SOC 项目设计经验
5. 精通AMBA协议
6. 良好的沟通能力和团队合作能力
Preferred to have:
1. ARM 子系统设计经验
2. AMBA 总线互联设计
3. DDR3/4, SD/SDIO设计经验
4. UART/SPI/IIC 设计调试经验
4. 芯片集成经验
北京 海淀区知春路 数字设计 ,数字验证工程师
ASIC数字电路设计验证工程师 (数字设计 或者数字验证都需要)
岗位职责:
1、根据系统组的需求,整理需求文档;
2、完成模块的设计文档;
3、完成模块的设计;
4、
完成模块的单元验证,给出测试报告/覆盖率分析报告;
5、协助系统验证工程师/FPGA测试工程师定位/解决问题。
任职要求:
1、微电子,计算机或者通信相关专业;
2、熟悉数字逻辑设计,掌握Verilog HDL,有相关软件实习应用经验;
3、熟悉验证,熟悉SystemVerilog;
4、了解综合/DFT/STA;
5、熟悉SoC架构、ARM体系、AMBA总线;
6、熟悉Synopsys开发工具;
7、掌握脚本语言如bash/perl,掌握Makefile;
8、良好的沟通能力和文档写作功底。
加分项:
1、熟悉VMM/OVM/UVM加分;
2、有通信背景加分;
3、有成功流片经历加分。
北京奥北科技园附近 8号线林萃桥
资深芯片设计工程师 Senior IC/ASIC/SOC Design Expert
Responsibilities:
IC Block design for all frontend phase
IC chip level design for all font-end phase
Architecture define
RTL implementation
Analysis and Optimization for performance
Analysis and Optimization for power
Analysis and Optimization for timing
Design flow: lint/synthesis/sta/formal check
Silicon debugging
Requirements:
BS / MS with 5+ years of experience in ASIC or FPGA design
Experience with CPU related IPs design are highly desirable
Experience as design lead for complex or high speed IPs
Experience with all phases of frontend architecture, design and validation
RTL Coding, Design Reviews, SYN, CDC, FEV, DFT insertion, ATPG analysis
Demonstrated work experience with timing Analysis, Area and Power optimizations, Performance Analysis, Debug ability and Security analysis, ECOs, and Post-Silicon Debug
Excellent knowledge of Verilog and popular EDA simulation & implementation tools
Good experience in scripting languages like Perl, Unix shell or similar languages
北京 双安商场附近
数字集成电路设计
岗位职责:
1. 设计验证数字接口模块
2. 设计验证DSP模块
3. IP集成,SOC设计
4. 设计验证时钟系统和控制系统
职位要求:
1. 熟练使用Verilog/VHDL做逻辑设计,有模块级原生设计能力
2. 熟悉DSP或者高速数字接口
3. 熟悉多时钟域和多电源域设计
4. 能描述模块SDC约束,熟悉数字前端流程,清晰理解概念
5. 有学习能力,能自我驱动,能良好沟通合作
数字前端实现工程师 (工作地点:北京/上海)
Responsibilities
1. Develop timing constraint and low power design constraint
2. Logic synthesis, STA, formal verification, low power check and DFT
3. Co-work with physical design team for timing closure
4. Improve digital front-end flow quality and efficiency
Qualifications
1. 3+ years’ experience
2. Experience with at least three successful chip tapeout
3. Proficient with synthesis, STA, formal verification, low power, DFT
4. Proficient with Design compiler, Prime time and Conformal LEC
5. Proficient with common Linux utility such as Shell, Perl
6. Good knowledge of digital logic design is a plus
7. Good knowledge of physical design is a plus
8. Good team player
数字验证实现工程师 (工作地点:北京/上海)
Responsibilities
1. Maintain/develop verification platform
2. Verification of chip level design
3. Provide verification support to design team
4. Improve verification quality and efficiency
Qualifications
1. 3+ years’ experience
2. Experience with at least one complete and successful chip verification
3. Proficient with Verilog, SystemVerilog and UVM/VMM
4. Proficient with C and script languages (Perl/Shell/Makefile/…)
5. Expert of EDA verification tools
6. Expert of verification methodologies