P&R Senior Engineer @合肥/深圳 简历发 hr@hi-talent.com 1、
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P&R Senior Engineer @合肥/深圳 简历发 hr@hi-talent.com
1、负责芯片的物理实现；
2、完成从RTL数字网表到GDS的相关数字后端工作：负责根据后端的实际PR情况，协助前端做design或sdc的修改以便timing能够更快的收敛，根据前端的修改，及时做好pre-maskECO与post-maskECO的工作.设计环境的建立,PNR library的生成及修改,芯片的布局,电源规划，单元放置，CTS，布线,时序分析及修正，功耗及电压完整性分析，信号完整性分析及修正，GDS输出及物理验证,DFM分析，寄生参数提取
3、布局布线，低功耗设计，EM及电压降分析；
4、静态时序分析，功耗分析，信号完整性分析；
5、物理验证，如DRC、ERC、LVS等；
1、3年以上数字后端相关设计经验；
2、熟悉STA/ICC/caliber/StarRC 等工具；
3、了解DFM/dummy/IO place/ESD/package model co-work/IR drop analysis and fix知识
IC Design Engineer@合肥 简历发 hr@hi-talent.com
IC前端设计及SOC系统工作，包括rtl coding，design综合，静态时序分析及收敛，芯片整合及验证相关工作
1、使用Synopsys/Cadence/Mentor公司如DC/DFT/STA/MBIST等tool进行前端flow
2、使用Perl, TCL, Awk和Sed等脚本语言进行部分tool job的整合以及相应report的分析
3、和前端IC设计师及后端物理工程师协同工作, 协调进行SOC时序收敛.
4、 规划SOC 低功耗设计
5、 对于DFT,定义IC测试规格与方法
5、编写相关脚本或进行MBIST, SCAN (包括stuck at, at speed), 边界扫描，模拟IP测试电路的生成，测试电路的验证，测试向量的生成
6、 与测试厂家合作，制定监视测试流程
1、 良好的沟通能力和团队合作精神
2、高度的责任心和敬业精神
3、较强的逻辑思维能力，善于发现问题，具有良好的自学能力和解决问题的能力
4、较强的英文能力
5、5年以上相关经验
Senior Modeling Engineer@合肥/深圳 简历发 hr@hi-talent.com
1、Good understanding of the device physics of bulk CMOS transistors and the correlation of the process technologies to the active and passive device’s performance,
2、Familiar with interconnect/device modeling,
3、Able to design and coordinate the test structure layouts and device matrices planning for SPICE modeling testchip development,
4、Create and update model release notes, model reference documents and application notes. Document any known limitations, issues, and solutions, in order to communicate relevant information on proper usage of the CMOS transistor model kits to customers.
1、8+ years modeling experience
2、Bachelor's Degree is required(microelectronics, Physics or related)
3、 Software programming skills in UNIX, LINUX and Windows environment(C/C++, Perl , etc) would be an advantage
4、 Familiar or has worked on foundry's PDK and usage for deep submicrometer or nanometer testchip tapeouts,
5、 Good communication skills.
Standard cell/SRAM library designer@合肥/深圳 简历发 hr@hi-talent.com
Responsible for verification, and release Standard Cell Libraries. Engage with internal teams to enable new validation checks for library,
Understand new EDA view requirements and define modeling requirements for new cells and libraries.
Continually improve library quality by defining and optimizing checks. Support designers using standard cell libraries.
负责验证，并发布标准元件库。与同事一起为元件库启用新的验证检查，
了解新的EDA要求，确定新的元件库的建模要求。
通过定义和优化检查，不断提高元件库的质量。帮助设计师使用标准元件库。
*Direct industry experience of at least 3 years or more.
* A solid understanding of logic design in transistor level.
* An understanding of transistor level device physics
* Experience with transistor level design of static circuits including state retaining elements like latches and flops
* An understanding of power, performance, and area tradeoffs
* An understanding of layout at the transistor level
* Experience designing or a solid understanding of standard cell architectures
*3年以上行业内工作经验。
*在晶体管级有充分的了解和逻辑设计。
*了解晶体管级物理器件。
*经验与晶体管级设计的静态电路，包括状态保持元素，如锁存和触发器
*了解电源、性能和区域的折衷
*了解在晶体管级的布局
*设计经验或对标准单元结构有充分的了解
Senior RF IC circuit design engineer@北京上海深圳 BJ/SH/SZ 简历发 hr@hi-talent.com
o Strong background in CMOS RF integrated circuit design
o Excellent understanding of transceiver architectures
o Good understanding of RF performance requirements for
o Strong analytical skills
o Excellent knowledge of RF system analysis and specification
o Experience with optimisation of RF circuit layout in advanced CMOS processes
oExperience with Cadence Analog Design Environment
o Experience with EM simulation tools
o Competent in usi
Best Regards
Jane.Jin 金娟
Principal Consultant & General Manager @ Hi-Talent Consulting Co.,Ltd.
上海芯得企业管理咨询有限公司
上海芯相会企业管理咨询有限公司
Mob: 18502155252
E-Mail: hr@hi-talent.com
微信： xindejane
QQ: 1600548210
Weibo: http://weibo.com/u/1716864892
website： www.hi-talent.cn
1、负责芯片的物理实现；
2、完成从RTL数字网表到GDS的相关数字后端工作：负责根据后端的实际PR情况，协助前端做design或sdc的修改以便timing能够更快的收敛，根据前端的修改，及时做好pre-maskECO与post-maskECO的工作.设计环境的建立,PNR library的生成及修改,芯片的布局,电源规划，单元放置，CTS，布线,时序分析及修正，功耗及电压完整性分析，信号完整性分析及修正，GDS输出及物理验证,DFM分析，寄生参数提取
3、布局布线，低功耗设计，EM及电压降分析；
4、静态时序分析，功耗分析，信号完整性分析；
5、物理验证，如DRC、ERC、LVS等；
1、3年以上数字后端相关设计经验；
2、熟悉STA/ICC/caliber/StarRC 等工具；
3、了解DFM/dummy/IO place/ESD/package model co-work/IR drop analysis and fix知识
IC Design Engineer@合肥 简历发 hr@hi-talent.com
IC前端设计及SOC系统工作，包括rtl coding，design综合，静态时序分析及收敛，芯片整合及验证相关工作
1、使用Synopsys/Cadence/Mentor公司如DC/DFT/STA/MBIST等tool进行前端flow
2、使用Perl, TCL, Awk和Sed等脚本语言进行部分tool job的整合以及相应report的分析
3、和前端IC设计师及后端物理工程师协同工作, 协调进行SOC时序收敛.
4、 规划SOC 低功耗设计
5、 对于DFT,定义IC测试规格与方法
5、编写相关脚本或进行MBIST, SCAN (包括stuck at, at speed), 边界扫描，模拟IP测试电路的生成，测试电路的验证，测试向量的生成
6、 与测试厂家合作，制定监视测试流程
1、 良好的沟通能力和团队合作精神
2、高度的责任心和敬业精神
3、较强的逻辑思维能力，善于发现问题，具有良好的自学能力和解决问题的能力
4、较强的英文能力
5、5年以上相关经验
Senior Modeling Engineer@合肥/深圳 简历发 hr@hi-talent.com
1、Good understanding of the device physics of bulk CMOS transistors and the correlation of the process technologies to the active and passive device’s performance,
2、Familiar with interconnect/device modeling,
3、Able to design and coordinate the test structure layouts and device matrices planning for SPICE modeling testchip development,
4、Create and update model release notes, model reference documents and application notes. Document any known limitations, issues, and solutions, in order to communicate relevant information on proper usage of the CMOS transistor model kits to customers.
1、8+ years modeling experience
2、Bachelor's Degree is required(microelectronics, Physics or related)
3、 Software programming skills in UNIX, LINUX and Windows environment(C/C++, Perl , etc) would be an advantage
4、 Familiar or has worked on foundry's PDK and usage for deep submicrometer or nanometer testchip tapeouts,
5、 Good communication skills.
Standard cell/SRAM library designer@合肥/深圳 简历发 hr@hi-talent.com
Responsible for verification, and release Standard Cell Libraries. Engage with internal teams to enable new validation checks for library,
Understand new EDA view requirements and define modeling requirements for new cells and libraries.
Continually improve library quality by defining and optimizing checks. Support designers using standard cell libraries.
负责验证，并发布标准元件库。与同事一起为元件库启用新的验证检查，
了解新的EDA要求，确定新的元件库的建模要求。
通过定义和优化检查，不断提高元件库的质量。帮助设计师使用标准元件库。
*Direct industry experience of at least 3 years or more.
* A solid understanding of logic design in transistor level.
* An understanding of transistor level device physics
* Experience with transistor level design of static circuits including state retaining elements like latches and flops
* An understanding of power, performance, and area tradeoffs
* An understanding of layout at the transistor level
* Experience designing or a solid understanding of standard cell architectures
*3年以上行业内工作经验。
*在晶体管级有充分的了解和逻辑设计。
*了解晶体管级物理器件。
*经验与晶体管级设计的静态电路，包括状态保持元素，如锁存和触发器
*了解电源、性能和区域的折衷
*了解在晶体管级的布局
*设计经验或对标准单元结构有充分的了解
Senior RF IC circuit design engineer@北京上海深圳 BJ/SH/SZ 简历发 hr@hi-talent.com
o Strong background in CMOS RF integrated circuit design
o Excellent understanding of transceiver architectures
o Good understanding of RF performance requirements for
o Strong analytical skills
o Excellent knowledge of RF system analysis and specification
o Experience with optimisation of RF circuit layout in advanced CMOS processes
oExperience with Cadence Analog Design Environment
o Experience with EM simulation tools
o Competent in usi
Best Regards
Jane.Jin 金娟
Principal Consultant & General Manager @ Hi-Talent Consulting Co.,Ltd.
上海芯得企业管理咨询有限公司
上海芯相会企业管理咨询有限公司
Mob: 18502155252
E-Mail: hr@hi-talent.com
微信： xindejane
QQ: 1600548210
Weibo: http://weibo.com/u/1716864892
website： www.hi-talent.cn