大神帮忙看看uvm报错

import uvm_pkg::*;
`include "uvm_macros.svh";
`include "my_driver1_vif_tr_field_sqr.sv"
`include "my_monitor.sv"
`include "my_transaction_field.sv"
`include "my_sequencer.sv"
`ifndef MY_AGENT__SV  
`define MY_AGENT__SV  
  
class my_agent extends uvm_agent ;  
   my_driver1     drv;  
   my_monitor    mon;  
    my_sequencer sqr;
     uvm_analysis_port #(my_transaction)  ap;
   function new(string name, uvm_component parent);  
      super.new(name, parent);  
   endfunction  
    
   extern virtual function void build_phase(uvm_phase phase);  
   extern virtual function void connect_phase(uvm_phase phase);  
  
   `uvm_component_utils(my_agent)  
endclass  
  
  
function void my_agent::build_phase(uvm_phase phase);  
   super.build_phase(phase);  
   if (is_active == UVM_ACTIVE) begin  
       sqr = my_sequencer::type_id::create("sqr",this);
       drv = my_driver1::type_id::create("drv", this);  
   end  
   mon = my_monitor::type_id::create("mon", this);  
endfunction  
  
function void my_agent::connect_phase(uvm_phase phase);  
   super.connect_phase(phase);  
   if(is_active==UVM_ACTIVE) begin
           drv.seq_item_port.connect(sqr.seq_item_export);  //line39
   end
    ap = mon.ap;
endfunction  
`endif
//////////////////////////////////////////////////////////
报错
# ** Error: (vsim-7065) my_agent_sqr.sv(39): Illegal assignment to class mtiUvm.uvm_pkg::uvm_port_base #(class mtiUvm.uvm_pkg::uvm_sqr_if_base #(class mtiUvm.uvm_pkg::uvm_sequence_item, class mtiUvm.uvm_pkg::uvm_sequence_item)) from class mtiUvm.uvm_pkg::uvm_seq_item_pull_imp #(class work.top_tb1_vif_env_sv_unit::my_transaction, class work.top_tb1_vif_env_sv_unit::my_transaction, class mtiUvm.uvm_pkg::uvm_sequencer #(class work.top_tb1_vif_env_sv_unit::my_transaction, class work.top_tb1_vif_env_sv_unit::my_transaction))
#    Time: 0 ps  Iteration: 0  Region: /top_tb1_vif_env_sv_unit File: /tb/sim/top_tb1_vif_env.sv
# ** Error: (vsim-8754) my_agent_sqr.sv(39): Actual input arg. of type 'class mtiUvm.uvm_pkg::uvm_seq_item_pull_imp #(class work.top_tb1_vif_env_sv_unit::my_transaction, class work.top_tb1_vif_env_sv_unit::my_transaction, class mtiUvm.uvm_pkg::uvm_sequencer #(class work.top_tb1_vif_env_sv_unit::my_transaction, class work.top_tb1_vif_env_sv_unit::my_transaction))' for formal 'provider' of 'connect' is not compatible with the formal's type 'class mtiUvm.uvm_pkg::uvm_port_base #(class mtiUvm.uvm_pkg::uvm_sqr_if_base #(class mtiUvm.uvm_pkg::uvm_sequence_item, class mtiUvm.uvm_pkg::uvm_sequence_item))'.

最后有`endif，是吧

贴一下下面几个class的代码
  my_driver1     drv;  
    my_sequencer sqr;

import uvm_pkg::*;
`include "uvm_macros.svh";
`include "my_transaction_field.sv"
`ifndef MY_DRIVER1__SV  
`define MY_DRIVER1__SV  
class my_driver1 extends uvm_driver#(my_transaction);  
  virtual my_if vif;
   `uvm_component_utils(my_driver1)  
   function new(string name = "my_driver1", uvm_component parent = null);  
      super.new(name, parent);  
      `uvm_info("my_driver1", "new is called", UVM_LOW);  
            if(!uvm_config_db#(virtual my_if)::get(this,"","vif",vif))
                `uvm_fatal("my_driver1","virtual if must be set for vif")
   endfunction  
   extern virtual task main_phase(uvm_phase phase);  
//    extern task drive_one_pkt(my_transaction tr);
endclass
  
task my_driver1::main_phase(uvm_phase phase);  
   vif.data <= 8'b0;  
   vif.valid <= 1'b0;  
   while(!vif.rst_n)  
      @(posedge vif.clk);  
    while(1) begin
    seq_item_port.get_next_item(req);
        drive_one_pkt(req);
        seq_item_port.item_done();
   end  
endtask  


`endif