Cadence上海招Sr AE Manager-Tensilica Processor
时间：12-12
整理：3721RD
点击：
1. 工作地点最好在上海，深圳也可以考虑。请直接将简历发至HR邮箱：cecilyl@cadence.com
2. 最好有带team的经验，英语和沟通要好
3. 技术关键词：Processor, DSP,ARM,MIPS
Sr AE Manager
Position Description:
As the manager of the APAC Tensilica IP Field Applications Engineering (FAE) Team, you will be responsible for driving technical and business campaign success with industry leading semiconductor and system companies. You will lead an IP AE team who’s role is to understand Cadence’s end customer’s IP needs and provide front line technical support in Pre-Sales and Post-Sales process. Strong management skills are required with a proven track record of recruiting top talent while retaining and developing existing talent. Intimate knowledge of the SoC development process, particularly as it relates to embedded cores and DSPs is a must.
The ideal candidate will:
oBe process orientated, and drive a high performance team culture
oBe a team player with strong problem solving and leadership skills
oHave strong customer facing skills to be able to establish technical & management credibility with the key technical decision makers
oChampion the customer needs and work with R&D and Marketing to develop competitive and creative technical solutions to win campaigns
oBe a key contributor driving product roadmap direction for our next generation products
oHave significant experience with complex SoC architecture and development flows
oHave experience and/or knowledge of one or more of Digital Audio, DSP, imaging or computer vision technologies.
oKnowledge of embedded processor or DSP architectures
oPrevious experience with Tensilica’s Xtensa processor core or derivatives is highly desirable
oExperience with DSP architectures desirable (ARM, MIPS, CEVA,Internal) – including architectural, software or HW/Debug related
oExperience of embedded software process for DSP development is beneficial, particularly for embedded DSP core architectures
oPossess excellent communication, presentation, and interpersonal skills
The role requires a strong technical background in SoC design flow from Architecture, Software development and debug, through to implementation. Experience with system architecture, and/or software or algorithm development in target markets highly desirable.
Position Requirements:
oBS degree in Electrical Engineering/Computer Science or related field
oAt least 10+ years of SoC and/or embedded software or DSP algorithm design experience
请直接将简历发至HR邮箱：cecilyl@cadence.com
2. 最好有带team的经验，英语和沟通要好
3. 技术关键词：Processor, DSP,ARM,MIPS
Sr AE Manager
Position Description:
As the manager of the APAC Tensilica IP Field Applications Engineering (FAE) Team, you will be responsible for driving technical and business campaign success with industry leading semiconductor and system companies. You will lead an IP AE team who’s role is to understand Cadence’s end customer’s IP needs and provide front line technical support in Pre-Sales and Post-Sales process. Strong management skills are required with a proven track record of recruiting top talent while retaining and developing existing talent. Intimate knowledge of the SoC development process, particularly as it relates to embedded cores and DSPs is a must.
The ideal candidate will:
oBe process orientated, and drive a high performance team culture
oBe a team player with strong problem solving and leadership skills
oHave strong customer facing skills to be able to establish technical & management credibility with the key technical decision makers
oChampion the customer needs and work with R&D and Marketing to develop competitive and creative technical solutions to win campaigns
oBe a key contributor driving product roadmap direction for our next generation products
oHave significant experience with complex SoC architecture and development flows
oHave experience and/or knowledge of one or more of Digital Audio, DSP, imaging or computer vision technologies.
oKnowledge of embedded processor or DSP architectures
oPrevious experience with Tensilica’s Xtensa processor core or derivatives is highly desirable
oExperience with DSP architectures desirable (ARM, MIPS, CEVA,Internal) – including architectural, software or HW/Debug related
oExperience of embedded software process for DSP development is beneficial, particularly for embedded DSP core architectures
oPossess excellent communication, presentation, and interpersonal skills
The role requires a strong technical background in SoC design flow from Architecture, Software development and debug, through to implementation. Experience with system architecture, and/or software or algorithm development in target markets highly desirable.
Position Requirements:
oBS degree in Electrical Engineering/Computer Science or related field
oAt least 10+ years of SoC and/or embedded software or DSP algorithm design experience
请直接将简历发至HR邮箱：cecilyl@cadence.com
Digital Audio, DSP, imaging or computer vision technologies.
Tensilica 不玩通讯了啊...
因为终端侧基于DSP的SDR方案不现实，大部分还都是基于RTL，DSP反而扮演了更多MCU的角色
基站侧的大玩家一只手就能数过来，市场容量就那么大
你是wang daqi?还是zeng youren
我是frankrick
这个职位汇报给谁呢?