上海欧美外企资深ASIC设计或者验证工程师4-年需要网络或者SOC背
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hi, ALL
上海欧美外企招聘资深ASIC设计与验证工程师 4+年以上(SALARY参考值 本科5-7年 25000+， 具体试个人资历定）
BACKGROUD： SOC/SWITCH/MAC/802.11/802.3/TCPIP/PCIE/USB
QQ： 2492202119 EMAIL: 2492202119@qq.com
JDS：
ASIC design for SoC
SOC and Switch verification
Wireless MAC verification
ASIC design for SoC
? ASIC design for WiFi SoC
? Participate in development of micro architecture specification and RTL implementation of digital blocks. Responsible for all phases of design including design, verification, synthesis, timing closure, power estimation, and DFT.
? Work closely with the USA teams
? Support chip tapeout and bring up
Requirements:
? At least 5 years ASIC design experience
? BS in Electrical Engineering (or equivalent) , MSEE is desired.
? Familiar with Verilog and System Verilog.
? Design experience with 802.11ac or 802.11n Wireless MAC.
? Design experience in DMA, CPU, PCIE, USB, Gigabit Ethernet, switch, bus protocol AXI, AHB.
? Working knowledge of networking protocols such as TCP/IP, 802.3, 802.11 a plus.
? Experience with Medium Access protocols a plus.
? Familiar with lint, CDC, formal verification methodologies.
? Understanding of basic DFT concepts.
? Hands on experience with synthesis and STA.
? FPGA emulation experience a plus
? Good communication and problem solving skills.
? Chip bring-up experience, including use of Logic Analyzer and Oscilloscope for debugging
SOC and Switch verification
1 SOC and Switch verification
2 Work closely with the USA teams
3 Support chip tape out and bring up
Requirements:
1 5+ years experience in ASIC Verification.
2 BS in Electrical Engineering (or equivalent) is a must have, MSEE is desired.
3 Working knowledge of networking protocols such as 802.3 and TCP/IP
4 Experience with switch engine verification.
5 System on Chip (SOC) Verification Experience, including AHB/AXI, CPU, Interface integration verification.
6 Experience verifying interfaces such as PCIe, Ethernet, DDR and USB.
7 Verification tool experience – Verilog, System-Verilog, Coverage Analysis.
8 Must be familiar with various scripting languages used in verification, including Perl, Csh, Make, etc.
9 Working knowledge of C programming language.
10 Must be expert in Verilog RTL language.
11 Must be familiar with the ASIC verification flow from feature identification to testbench development and through final tapeout sign-off.
12 FPGA emulation experience a plus.
13 Chip bring-up experience, including use of Logic Analyzer and Oscilloscope for debugging
Wireless MAC verification
The Role:
1 Wireless MAC verification
2 Work closely with the USA teams
3 Support chip tape out and bring up
Requirements:
1 5+ years experience in ASIC Verification.
2 BS in Electrical Engineering (or equivalent) is a have, MSEE is desired.
3 Working knowledge of networking protocols such as 802.11, 802.3 and TCP/IP.
4 Working experience with Medium Access protocols.
5 Verification tool experience – Verilog, System-Verilog, Coverage Analysis.
6 Must be familiar with various scripting languages used in verification, including Perl, Csh, Make, etc.
7 Experience verifying interfaces such as PCIe, Ethernet, DDR, USB a plus.
8 Working knowledge of C programming language.
9 Must be expert in Verilog RTL language.
10 Must be familiar with the ASIC verification flow from feature identification to testbench development and through final tapeout sign-off.
11 FPGA emulation experience a plus.
12 Chip bring-up experience, including use of Logic Analyzer and Oscilloscope for debugging
上海欧美外企招聘资深ASIC设计与验证工程师 4+年以上(SALARY参考值 本科5-7年 25000+， 具体试个人资历定）
BACKGROUD： SOC/SWITCH/MAC/802.11/802.3/TCPIP/PCIE/USB
QQ： 2492202119 EMAIL: 2492202119@qq.com
JDS：
ASIC design for SoC
SOC and Switch verification
Wireless MAC verification
ASIC design for SoC
? ASIC design for WiFi SoC
? Participate in development of micro architecture specification and RTL implementation of digital blocks. Responsible for all phases of design including design, verification, synthesis, timing closure, power estimation, and DFT.
? Work closely with the USA teams
? Support chip tapeout and bring up
Requirements:
? At least 5 years ASIC design experience
? BS in Electrical Engineering (or equivalent) , MSEE is desired.
? Familiar with Verilog and System Verilog.
? Design experience with 802.11ac or 802.11n Wireless MAC.
? Design experience in DMA, CPU, PCIE, USB, Gigabit Ethernet, switch, bus protocol AXI, AHB.
? Working knowledge of networking protocols such as TCP/IP, 802.3, 802.11 a plus.
? Experience with Medium Access protocols a plus.
? Familiar with lint, CDC, formal verification methodologies.
? Understanding of basic DFT concepts.
? Hands on experience with synthesis and STA.
? FPGA emulation experience a plus
? Good communication and problem solving skills.
? Chip bring-up experience, including use of Logic Analyzer and Oscilloscope for debugging
SOC and Switch verification
1 SOC and Switch verification
2 Work closely with the USA teams
3 Support chip tape out and bring up
Requirements:
1 5+ years experience in ASIC Verification.
2 BS in Electrical Engineering (or equivalent) is a must have, MSEE is desired.
3 Working knowledge of networking protocols such as 802.3 and TCP/IP
4 Experience with switch engine verification.
5 System on Chip (SOC) Verification Experience, including AHB/AXI, CPU, Interface integration verification.
6 Experience verifying interfaces such as PCIe, Ethernet, DDR and USB.
7 Verification tool experience – Verilog, System-Verilog, Coverage Analysis.
8 Must be familiar with various scripting languages used in verification, including Perl, Csh, Make, etc.
9 Working knowledge of C programming language.
10 Must be expert in Verilog RTL language.
11 Must be familiar with the ASIC verification flow from feature identification to testbench development and through final tapeout sign-off.
12 FPGA emulation experience a plus.
13 Chip bring-up experience, including use of Logic Analyzer and Oscilloscope for debugging
Wireless MAC verification
The Role:
1 Wireless MAC verification
2 Work closely with the USA teams
3 Support chip tape out and bring up
Requirements:
1 5+ years experience in ASIC Verification.
2 BS in Electrical Engineering (or equivalent) is a have, MSEE is desired.
3 Working knowledge of networking protocols such as 802.11, 802.3 and TCP/IP.
4 Working experience with Medium Access protocols.
5 Verification tool experience – Verilog, System-Verilog, Coverage Analysis.
6 Must be familiar with various scripting languages used in verification, including Perl, Csh, Make, etc.
7 Experience verifying interfaces such as PCIe, Ethernet, DDR, USB a plus.
8 Working knowledge of C programming language.
9 Must be expert in Verilog RTL language.
10 Must be familiar with the ASIC verification flow from feature identification to testbench development and through final tapeout sign-off.
11 FPGA emulation experience a plus.
12 Chip bring-up experience, including use of Logic Analyzer and Oscilloscope for debugging
你和楼下撞楼了
又是switch又是802.11肯定是qca喽，进去等着领裁员package可以的。
※ 发自: 轻松水木
不是