asic summary 简历发ic@hi-talent.com

ASIC 简历发ic@hi-talent.com
Positions summary:
1. Multimedia Arch/Infrastructure Engineer
2. Soc ASIC Desgin
3. ASIC Physical Design engineer
4. ASIC Design Engineer—Xbar
5. Senior Power Methodology Engineer
6. System Design Software Engineer



Job Description:

1.   Multimedia Arch/Infrastructure Engineer
RESPONSIBILITIES:
- We are looking for world class programmers to develop the core infrastructure for modeling, analysis, verification and debugging in the development of multimedia IP.
- The candidates will work with a group of architects to design and develop environment for different abstraction level of models in multimedia team.
- The candidates will develop regression system of simulation, validation, debug of IP functionality and performance.
- The candidates will develop tools for image gilding, image view, image compare and GUI-based test tuning.

MINIMUM REQUIREMENTS:
- Bachelor Degree or higher majoring in CS/EE/Mathematics or relevant fields.
- Strong C/C++ programming ability. Scripting language (Perl, Python) experience is a must.
- GUI development on Linux, Windows platform is a plus.
- Digital image signal processing experience is a plus.
- Experience of team leading to develop middle scale SW product is a plus.
- Well organized problem solving capability and communication skills
- Strong software debugging capability and experiences
- Proactive, creative and a team player
- Excellent English writing for engineering documentation, English oral well enough to attend meetings

2.   SOC ASIC Design
The NVIDIA System-On-Chip (SOC) group is looking for a top ASIC engineer with interest in RTL design, integration, Synthesis and verification. The ideal candidate for this position has prior experience in putting together top-level RTL of complex SOCs and has great passion for methodologies and automation solutions that enable creating complex SOCs in the least amount of time.

In this position, you will have the opportunity to be responsible for creating complex GPUs and SOCs and interface between unit-level, Physical Design, CAD, Package Design, Software, DFT and other teams. Additionally, you will be involved with defining and creating methodologies that create more efficient and flexible SOCs in future.

MINIMUM REQUIREMENTS:
- BS or MS (preferred) in EE
- Experience in RTL design (Verilog), verification and synthesis
- Strong coding skills in Perl or other industry-standard scripting languages
- Prior experience in implementing System-On-Chip is a plus
- Prior experience in RTL related automation is a plus
- Ability to interface with many groups

3.ASIC Physical Design engineer
As a senior member of our ASIC-PD team, you'll be working on streamlining the chip infrastructure process across product designs, focusing on full chip layout planning (partitioning, planning clock distribution and other structure, methodology), partition/full chip timing closure (primetime scripts, other tools, etc) and gate-level design of high-speed logic
RESPONSIBILITIES:
1.Chip integration and netlist generation
2.Synthesis, Formal verification, netlist quality check
3.Work in conjunction with Place and Route Engineers to achieve timing closure for both partition level and full chip level
4.Develop and enhance entire timing flow from frontend (pre-layout) to backend (post-layout) at both chip and block level.
5.Develop custom timing scripts using tcl/primetime for clock skew analysis, special circuits such as clock dividers, core logic <-> IO macros interfaces such as PCI-E, Frame-Buffer/Memory, TMDS, etc.
6.Develop flow to physically partition and floorplan the entire chip.
7.Develop scripts for performing ECO's.

MINIMUM REQUIREMENTS:
1.BS or MS in Electrical Engineering or Computer Science
2.Above 3 years of relevant ASIC experience ideally with a focus in the chip integration /synthesis/formal and timing closure
3.Excellent scripts skills
4.Excellent written and verbal communication skills in English
5.Ability to multiplex many issues, set priorities, and work in a team environment
6.Keep up to date with leading edge technologies

4.ASIC Design Engineer--XBar
Required Skills:
1.       Ability to communicate technical subjects in both written and oral form
2.       Strong Verilog and Perl programing skills
3.       Good Understanding of RTL synthesis and simulation tools and gate level debug
4.       Good Understanding of low power design technology
5.       Experience with Simulation Tools ¨C Cadence NCSIM, Synopsys VCS or similar
6.       Experience with Synthesis Tools ¨C Synopsys Design Compiler /DCT/DC Ultra or similar
7.       Experience with large scale design and multi-system verification
8.       Excellent written and spoken English Language
9.       Self-motivated and work patiently
Desirable Skills:
1.       Some appreciation of Makefile, Shell and C++ programing skills
2.       Good knowledge and experience with multi-clock design
3.       Good knowledge and experience of internal bus protocol and arbitration design
4.       Experience of scripting working environment
5.       Ability to work with diverse and geographically dispersed team

5. Senior Power Methodology Engineer
Power methodology team is responsible for researching power expenditures and workload efficiency to identify architectural, micro-architectural strategies to improve power efficiency of the next generation GPU and TEGRA chips.
Responsibilities:
·         Develop the power flow to automate the power expenditures measurement.
·         Evaluate new low-power technologies and provide feedback to power ARCH team to improve chip power efficiency on architectural level.
·         Support GPU/TEGRA RTL designers using the power flow to do the power scrubbing work and improve their power efficiency on micro-arch level.
·         Understand and perform block level and chip-level power analysis.
Requirements:
·         MSEE/MSCS with at least 5 years working experience on ASIC related areas.
·         Familiar with advanced low power techniques and high speed clocking desired.
·         Experience in low power ASIC design/verification.
·         Programming languages: Strong Verilog (or VHDL), Perl, Tcl is must,  C ++ is a plus.
·         Tool Familiarity: PTPX, Synopsys Design Compiler, VCS simulation tool is must, Power Artist is a plus.
·         Excellent communication skills and ability to be good at teamwork.
·         Excellent English writing/speaking skills
6. System Design Software Engineer
Job Description/Qualifications:
We are looking for world class programmers to develop the core infrastructure for modeling, analysis, verification and debugging in the development of large scale graphics chips, which enables NVIDIA's driver stack, applications, tests and studies to all run unchanged on all functional, diagnostic, and performance models, simulations, emulations and silicon for all of NVIDIA's graphics chips.
- The candidates will work with a group of architects to design and develop proprietary internal tools for the visualization, analysis, and debug and verification of tests and applications on various functional and performance simulations of future chips.
- The candidates will have opportunities to get involved in cutting-edge GPGPU applied architecture design, verification and optimization, including porting commercial applications to test bench, finding out performance hotspots and data mining for performance analysis.

REQUIREMENTS:
- Bachelor’s Degree or higher majoring in CS/EE/Mathematics or relevant fields.
- Strong C/C++ programming ability. Scripting language (Perl, Python, Ruby) experience is a plus.
- Well organized problem solving capability and communication skills
- Strong software debugging capability and experiences
- Proactive, creative and a team player
- Excellent English writing for engineering documentation, English oral well enough to attend meetings
- Experience in the following areas is a plus:
- Microprocessor architecture design & verification
- 3D graphics (d3d or OpenGL) application development
- Multimedia (video, image processing, visualization) application development
- System level programming experience in OS, compiler, driver, tools, virtual memory system, etc.
- Parallel computing/CUDA/OpenCL/HPC development


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Scarlett.Jane.Jin
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