一步时钟域脉冲信号捕获问题

有一个脉冲信号，宽度为一个clk周期，从A时钟域到B时钟域，A与B异步，且B频率略低于A；请教这种情况，如何在B时钟域内正常捕获并还原这个单clk周期的脉冲信号？
两级锁存肯定是不行的，有哪些经典的电路结构，适合FPGA用。

pulse to level, then sync the level signal, finally, change the synced level signal to pulse. but it has pre-reqirement that the pulse-to-pulse signal interval must be very distant.
or use the fifo structure