上海InvenSense新出的职位，验证与设计
时间：12-12
整理：3721RD
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我们已经进行了二轮的招聘，最近又出了新职位，RTL design和验证方向，欢迎大家踊跃投递简历~~
由于每个职位的竞争比较激烈，所以很多优秀的应聘者未能在前二轮中获胜，不过你们已经进入了我们的候选者名单中，会在每个新职位出来时优先列入考虑范围，所以不需要再重复投递简历，如果我们觉的合适的话，会有电话跟你联络的。
有关InvenSense的介绍，可以登录：www.invensense.com 获取更加详细的了解。
中文名称 ：应美盛半导体科技（上海）有限公司
办公地点 ：上海张江高科技园区
企业性质 ：美资外企，纽交所上市企业（INVN）
主营业务 ：运动检测和音频处理相关的硅传感器（MEMS）以及ASIC/SoC芯片，包括陀螺仪，加速度计，硅麦克风等
1.Digital RTL Design and Implementation (synthesis \ DFT \ Timing Closure) Engineer
Location: Shanghai
Responsibilities:
• Digital RTL design and implementation for mixed signal/SoC ICs
• Starting from Verilog RTL, and using industry standard tools, implement the design through synthesis, floor planning, clock tree synthesis and routing.
Block level RTL design.
• Perform static timing analysis(STA) and help to identify and fix timing problems in the design
• Perform design for test (DFT) and test pattern generation (ATPG).
• Close interaction with analog/mixed signal designers.
Qualifications:
• Master's degree with at least 3 years of experience with digital RTL design and flow.
• Experience with RTL design
• Experience with one of the below area
o Synthesis,
o Timing analysis / Timing Closure
o DFT
• Knowledge of Audio processing or signal processing or SOC design is a big plus
• Knowledge of scripting languages such as Perl and Tcl is a plus.
• Good English written and verbal communication skills.
• Excellent communication and team-oriented skills.
• Self-motivated individual willing to take ownership and responsibility.
2. Digital Verification Engineer (mixed signal/SoC)
Location: Shanghai
Responsibilities:
• Verification with Verilog / System Verilog / UVM
• Setup verification testbench in module level and Chip level, define and execute verification plan with full functional coverage.
• Doing simulation in Gate Level and doing co-simulation with analog designer.
• Interact with design team to achieve design quality and meet schedule target.
• Document and review detail test plans, testbench and meet verification goals.
• Support silicon evaluation effort.
Qualifications:
• Master's degree with 5+ years of experience with SoC/Mix-signals IC verification
• Knowledge of OVM/VMM/UVM
• Knowledge of Audio processing or signal processing or SOC design is a big plus.
• Familiar with digital & mixed signal verification tools, such as NC-verilog/Verdi/Vplan.
• Familiar with Verilog/ System Verilog/ System C language.
• Knowledge of scripting languages such as Perl and Tcl is a plus.
• Good English written and verbal communication skills.
• Excellent communication and team-oriented skills.
• Self-motivated individual willing to take ownership and responsibility.
简历请发送：
ypan@invensense.com
格式如下：
姓名_性别_学校_学历_工作年限_职位_现公司名.docx/.pdf
请将中文简历和英文简历分开。
由于每个职位的竞争比较激烈，所以很多优秀的应聘者未能在前二轮中获胜，不过你们已经进入了我们的候选者名单中，会在每个新职位出来时优先列入考虑范围，所以不需要再重复投递简历，如果我们觉的合适的话，会有电话跟你联络的。
有关InvenSense的介绍，可以登录：www.invensense.com 获取更加详细的了解。
中文名称 ：应美盛半导体科技（上海）有限公司
办公地点 ：上海张江高科技园区
企业性质 ：美资外企，纽交所上市企业（INVN）
主营业务 ：运动检测和音频处理相关的硅传感器（MEMS）以及ASIC/SoC芯片，包括陀螺仪，加速度计，硅麦克风等
1.Digital RTL Design and Implementation (synthesis \ DFT \ Timing Closure) Engineer
Location: Shanghai
Responsibilities:
• Digital RTL design and implementation for mixed signal/SoC ICs
• Starting from Verilog RTL, and using industry standard tools, implement the design through synthesis, floor planning, clock tree synthesis and routing.
Block level RTL design.
• Perform static timing analysis(STA) and help to identify and fix timing problems in the design
• Perform design for test (DFT) and test pattern generation (ATPG).
• Close interaction with analog/mixed signal designers.
Qualifications:
• Master's degree with at least 3 years of experience with digital RTL design and flow.
• Experience with RTL design
• Experience with one of the below area
o Synthesis,
o Timing analysis / Timing Closure
o DFT
• Knowledge of Audio processing or signal processing or SOC design is a big plus
• Knowledge of scripting languages such as Perl and Tcl is a plus.
• Good English written and verbal communication skills.
• Excellent communication and team-oriented skills.
• Self-motivated individual willing to take ownership and responsibility.
2. Digital Verification Engineer (mixed signal/SoC)
Location: Shanghai
Responsibilities:
• Verification with Verilog / System Verilog / UVM
• Setup verification testbench in module level and Chip level, define and execute verification plan with full functional coverage.
• Doing simulation in Gate Level and doing co-simulation with analog designer.
• Interact with design team to achieve design quality and meet schedule target.
• Document and review detail test plans, testbench and meet verification goals.
• Support silicon evaluation effort.
Qualifications:
• Master's degree with 5+ years of experience with SoC/Mix-signals IC verification
• Knowledge of OVM/VMM/UVM
• Knowledge of Audio processing or signal processing or SOC design is a big plus.
• Familiar with digital & mixed signal verification tools, such as NC-verilog/Verdi/Vplan.
• Familiar with Verilog/ System Verilog/ System C language.
• Knowledge of scripting languages such as Perl and Tcl is a plus.
• Good English written and verbal communication skills.
• Excellent communication and team-oriented skills.
• Self-motivated individual willing to take ownership and responsibility.
简历请发送：
ypan@invensense.com
格式如下：
姓名_性别_学校_学历_工作年限_职位_现公司名.docx/.pdf
请将中文简历和英文简历分开。