verisilicon（北京） recruiting physical design（后端）/STA
时间：12-12
整理：3721RD
点击：
职位描述:
Design Implementation (Back End/Physical Design) staff Engineer / Sr. Engineer
设计实现(后端/物理实现)工程师/高级工程师
JobResponsibility:
1.Responsible for SDC and UPF/CPF development and debug
2.Focus on design floor planning, power planning, IO planning, placement & CTS and routing, handling timing and congestion issue during project implementation
3.IP level and chip level physical verification and DFM rule checking
4.Power analysis and IR drop/EM analysis for both static and dynamic
5.Strong capability in timing analysis, and independently handle all timing issues from netlist/RTL to GDS process
6.Responsible for timing signoff for all functional modes and concerns, and work closely with DFT engineer for scan modes timing closure
7.Work closely with package team and IO team regarding IO placement to address IO ESD, SSO and chip power supplement concerns
8.Communicate with customer as well as AE or sales
Requirement :
1.Bachelor’s degree or above in EE
2.Skill in csh/perl/tcl
3.For Senior Engineer position, 2+ years work experience in relevant areas is required
4.Good knowledge in at least one of the following disciplines: high speed chip P&R skills, advance node chip P&R, hierarchical flow or low power P&R implementation, physical layout & verification
5.Rich experience on timing/noise violation fixing and CTS tree synthesis
6.Good understanding about entire development flow of IC design
7.Good understanding about FE design, process, package, testing, etc.
8.Fluent in both English and Chinese
9.Self motivated, good communication skill and team work spirit
职位描述
1. 负责SDC以及 UPF/CPF的开发和调试
2. 主要从事项目实施阶段的平面布置图设计，功耗规划，IO规划，布局布线 和CTS, 解决时序和拥塞问题
3. IP层面和芯片层面的物理验证，检查DFM规则
4. 静态和动态功耗分析、IR压降/ EM分析
5. 擅长时序分析，独立解决从网表/RTL到GDS开发过程中的所有时序问题
6. 负责所有功能模式的时序签收，配合DFT工程师完成扫描模式的时序收敛
7. 配合封装团队和IO团队妥善布局IO， 解决IO ESD、SSO和芯片供电问题
8. 与客户、应用工程师和销售人员沟通交流相关事宜
应聘要求
1. 电子工程本科或以上学历
2. csh/perl/tcl脚本编写技巧
3. 申请高级工程师职位须具备2年以上相关工作经验
4. 下述领域中至少熟练掌握其中一项：高速芯片P＆R，先进制成的芯片P＆R，分层设计流程，低功耗P＆R实现，物理布局及验证
5. 善于排除时序/噪音错误、合成CTS树，经验丰富
6. 通晓IC设计的整个开发流程
7. 通晓前端设计，工艺，封装，测试等
8. 中英文流利
9. 勤奋踏实，良好的沟通能力和团队合作精神
北京公司地址：
北京市海淀区东北旺西路8号中关村软件园信息中心大厦A座一层A106
resume send to: tiger.zhang@verisilicon.com
Design Implementation (Back End/Physical Design) staff Engineer / Sr. Engineer
设计实现(后端/物理实现)工程师/高级工程师
JobResponsibility:
1.Responsible for SDC and UPF/CPF development and debug
2.Focus on design floor planning, power planning, IO planning, placement & CTS and routing, handling timing and congestion issue during project implementation
3.IP level and chip level physical verification and DFM rule checking
4.Power analysis and IR drop/EM analysis for both static and dynamic
5.Strong capability in timing analysis, and independently handle all timing issues from netlist/RTL to GDS process
6.Responsible for timing signoff for all functional modes and concerns, and work closely with DFT engineer for scan modes timing closure
7.Work closely with package team and IO team regarding IO placement to address IO ESD, SSO and chip power supplement concerns
8.Communicate with customer as well as AE or sales
Requirement :
1.Bachelor’s degree or above in EE
2.Skill in csh/perl/tcl
3.For Senior Engineer position, 2+ years work experience in relevant areas is required
4.Good knowledge in at least one of the following disciplines: high speed chip P&R skills, advance node chip P&R, hierarchical flow or low power P&R implementation, physical layout & verification
5.Rich experience on timing/noise violation fixing and CTS tree synthesis
6.Good understanding about entire development flow of IC design
7.Good understanding about FE design, process, package, testing, etc.
8.Fluent in both English and Chinese
9.Self motivated, good communication skill and team work spirit
职位描述
1. 负责SDC以及 UPF/CPF的开发和调试
2. 主要从事项目实施阶段的平面布置图设计，功耗规划，IO规划，布局布线 和CTS, 解决时序和拥塞问题
3. IP层面和芯片层面的物理验证，检查DFM规则
4. 静态和动态功耗分析、IR压降/ EM分析
5. 擅长时序分析，独立解决从网表/RTL到GDS开发过程中的所有时序问题
6. 负责所有功能模式的时序签收，配合DFT工程师完成扫描模式的时序收敛
7. 配合封装团队和IO团队妥善布局IO， 解决IO ESD、SSO和芯片供电问题
8. 与客户、应用工程师和销售人员沟通交流相关事宜
应聘要求
1. 电子工程本科或以上学历
2. csh/perl/tcl脚本编写技巧
3. 申请高级工程师职位须具备2年以上相关工作经验
4. 下述领域中至少熟练掌握其中一项：高速芯片P＆R，先进制成的芯片P＆R，分层设计流程，低功耗P＆R实现，物理布局及验证
5. 善于排除时序/噪音错误、合成CTS树，经验丰富
6. 通晓IC设计的整个开发流程
7. 通晓前端设计，工艺，封装，测试等
8. 中英文流利
9. 勤奋踏实，良好的沟通能力和团队合作精神
北京公司地址：
北京市海淀区东北旺西路8号中关村软件园信息中心大厦A座一层A106
resume send to: tiger.zhang@verisilicon.com
由于北京TEAM 是新成立的 所以暂时不招JUNIOR ENGINEE。 只招： SENIOR/ STAFF / SENIOR STAFF。 好多人站内问我，在此解释一下。