上海ASIC Design Engineer,ASIC Verification Engineer

 Q6JD_ASIC_Design.docx

 Q7JD_ASIC_Verification.docx
[上海][美资公司][ASIC Design Engineer |ASIC Verification Engineer]要求Master 5 years+, 具有wifi，蓝牙项目经验,熟悉USB/PCIE接口
联系人:张小嫚儿(Candice)-小猎一枚，请大家多多关照    
QQ: 192431083(192431083@qq.com)
JD:
The candidate for ASIC Design Engineer should meet the following criteria:
The Role:
o    ASIC design and verification
o    Work closely with the California teams
o    Support chip tape out and bring up
Requirements:
o    5+ years experience in ASIC design
o    BS in Electrical Engineering (or equivalent) is a must have, MSEE is desired
o    System on Chip (SOC) Integration Experience, including AHB/AXI, CPU, Interface integration
o    Experience with WIFI or related wireless technology (i.e. WIMAX, 3G, LTE, etc.) is a plus
o    Experience with interfaces such as PCIe, Ethernet, DDR, USB
o    Working knowledge of networking protocols such as TCP/IP, 802.3, 802.11
o    Working knowledge of C programming language
o    Experience with Medium Access protocols a plus
o    Must be expert in Verilog RTL language
o    Must be familiar with the ASIC design flow from RTL through synthesis, including the tool flow.
o    Verification experience – Verilog, System-Verilog, Coverage Analysis
o    FPGA emulation experience
o    Chip bring-up experience, including use of Logic Analyzer and Oscilloscope for debugging
联系人:Candice Zhang        QQ: 192431083    Email: 192431083@qq.com
TEL:  021 63511401 转 806(上海)
----------------------------------------------------------------------------------------------
The candidate for ASIC Verification Engineer should meet the following criteria:
The Role:
o    ASIC design and verification
o    Work closely with the California teams
o    Support chip tape out and bring up
Requirements:
o    5+ years experience in ASIC Verification
o    BS in Electrical Engineering (or equivalent) is a must have, MSEE is desired
o    System on Chip (SOC) Verification Experience, including AHB/AXI, CPU, Interface integration verification
o    Very familiar with verification languages – Verilog, System-Verilog, and VMM
o    Test plan and test case documentation
o    Functional coverage and code coverage analysis
o    Must be familiar with various scripting languages used in verification, including Perl, Csh, Make, etc.
o    Experience verifying interfaces such as PCIe, Ethernet, DDR, USB
o    Working knowledge of networking protocols 802.3 and 802.11, especially Medium Access Control and TCP/IP
o    Working knowledge of C programming language
o    Must be familiar with the ASIC verification flow from feature identification to test bench development and through final tape out sign-off
o    FPGA emulation experience a plus
o    Chip bring-up experience, including use of Logic Analyzer and Oscilloscope for debugging
联系人:Candice Zhang        QQ: 192431083    Email: 192431083@qq.com
TEL:  021 63511401 转 806(上海)