电流舵DAC版图求指教

各种大神好，小弟想请问各位电流舵型DAC版图上的一些知识。文章里边说把电流源分成4份16份的是什么意思没怎么看明白还有一堆数表什么的，谁能简单介绍下，然后就是关于版图匹配镜像电流源画法的注意事项的一些参考资料文章什么的想让各位帮忙推荐一些。谢谢各位了！

switching schemes, or switching sequence
pls do some work before asking...

真不是不愿意做，那些文章反复看了好几遍真是不明白这个版图布局讲的到底是啥，要不您帮忙几句话给概括一下剩下的我自己看看。或者您给提示几个比较不错的paper？我愿意do any work

我刚才用scholar.google.com搜索了switching sequence DAC，
得到的几个参考文献都是很经典的，基本都能够解答你提出的问题。。。
ref 1.
Switching sequence optimization for gradient error compensation in thermometer-decoded DAC arrays
Y Cong, RL Geiger - Circuits and Systems II: Analog and Digital …, 2000 - ieeexplore.ieee.org
Abstract This paper discusses switching schemes for gradient error compensation in unary
(thermometer-decoded) arrays of digital-to-analog converters (DACs). The absolute lower
bound of integral nonlinearity (INL) by optimizing switching sequences is established and ...
ref 2.
A 14-bit 200-MHz current-steering DAC with switching-sequence post-adjustment calibration
T Chen, GGE Gielen - Solid-State Circuits, IEEE Journal of, 2007 - ieeexplore.ieee.org
Abstract In this paper, a novel calibration method for high-accuracy current-steering DACs is
presented. Different from traditional calibration methods which achieves the calibration by
adjusting the current values of the current sources, our method does the calibration by ...
ref 3.
A 14-bit intrinsic accuracy Q< sup> 2</sup> random walk CMOS DAC
GAM Van der Plas, J Vandenbussche… - Solid-State Circuits, …, 1999 - ieeexplore.ieee.org
... have a residual error below the average (negative DNL). This leads us to the choice
of the switching sequence for the 8–6 segmented 14-bit DAC. From a test chip, an error
profile of the 256 unary current sources has been estimated. ...
ref 4
A 12-bit intrinsic accuracy high-speed CMOS DAC
J Bastos, AM Marques, MSJ Steyaert… - Solid-State Circuits, …, 1998 - ieeexplore.ieee.org
... On the other hand, the switching sequence combined with the 2-D mirroring of the
DAC's implements in the overall arrangement a hierarchical symmetrical switching
sequence that compensates and averages 2-D parabolic errors. ...

ref:A 14-bit intrinsic accuracy Q< sup> 2</sup> random walk CMOS DAC
GAM Van der Plas, J Vandenbussche… - Solid-State Circuits, …, 1999 - ieeexplore.ieee.org
The linearity of the DAC is now determined by the accumulation
of these residual errors when the current sources are
switched on one by one. It is essential to keep the accumulated
error as low as possible, or in other words, to turn on current
sources in a sequencesuch that the systematic error residues
are not accumulating. Note that some current sources have a
residual error higher than average (positive DNL) while others
have a residual error below the average (negative DNL).
Ref:Switching sequence optimization for gradient error compensation in thermometer-decoded DAC arrays
Y Cong, RL Geiger - Circuits and Systems II: Analog and Digital …, 2000 - ieeexplore.ieee.org
Optimizing switching schemes can reduce the nonlinearity
due to gradient errors. This potential has been seen in many
current-steering DAC designs [1]–[6]. A switching scheme
is actually a layout technique. In a current-steering DAC, the
switching scheme determines the interconnection between
the outputs of the thermometer decoder/latch and the control
terminals of the switches in the current matrix.