AMD内部推荐 又出了新职位 DE/DV/PD/drvier/...
时间：12-12
整理：3721RD
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2年以上工作经验的，设计、SOC、验证、PD、driver的都需要
之前内推的都是DE和DV 现在有些新的职位，有兴趣的多关注
北京职位已满
内推 有兴趣的发邮件到zzxgxcdma@163.com
地点：上海
title:
3.Front-end ASIC design CAD engineer
4.Windows 2D/3D graphics driver Senior/MTS/section manager
5.MTS/SMTS of Physical Design
6.Sr. Physical Design Engineer
7.MTS DV Engineer (CPU background)
8.MTS DV Engineer (SoC Emulation DV)
9.MTS/SMTS of DFT
10. Sr. Windows/Linux Graphic Base Driver Engineer
地点:北京
title:
地点:苏州
title:
DB & Application Specialist
下面是部分JD：
Sr. Fro-end ASIC Design CAD engineer
Position Summary
? Participate in the design and implementation of the leading edge, front-end ASIC design flow
? Participate in the research of Design Methodology to improve automation and productivity to produce AMD's new high-quality cutting-edge APU and GPU products
? Technical support and programming
? Interface with EDA vendors on technology
Essential Requirements/Qualifications:
1. Major in EE, CS or related, Master Degree with 3+ years or Bachelor with 5+ years working experience
2. Experience in Front-end digital design and VerilogHDL is required
3. Good programming skill with one or more languages (e.g. Tcl, Perl, python, c/c++, etc.) in Unix/Linux and a strong desire to automate flow
4. Familiar with SRAM design and behaviour is a plus
5. Familiar with one or more ASIC flows (logic synthesis, STA etc.) and usage of related EDA tools is a plus
6. Good written and spoken English
7. Good communication skills and be able to work both independently and in a team
Windows 2D/3D graphics driver Senior/MTS engineer
DESCRIPTION OF DUTIES IN ADDITION TO THOSE IN JOB DESCRIPTION:
- Develop and Maintain the AMD GPU DirectX Driver.
- Work with HW design team to tune DirectX Driver performance.
PREFERRED EXPERIENCE:
- Master/Ph.D Degree of Computer Science, Mathematics or Electronic Engineering.
- 3+ years experience working in Graphics Driver under Microsoft Windows.
- 5+ years experience of C/C++ programming.
- Knowledge of DirectX application developing under Microsoft Windows.
- Knowledge of Computer Graphics.
- Knowledge of x86 assembler language and x86/x64 CPU instructions.
- Knowledge of PC architecture.
Physical Design Engineer
这个JD是SMTS的 SR MTS的经验年限要求2+ 5+左右
Job Description:
Work with global Front-End design team and physical design team for large scale ASIC chip physical implementation. Focus on physical design of deep sub-micron GPU chips including block level (full chip) floor planning, timing closure, place&route, physical verification etc. The individual is expected to be an expert in multiple aspects in PD areas and provide technically leadership to the engineering team. The individual is also expected to be accountable for project delivery.
Job Requirement:
1. MSEE with 8+ years or Bachelor with 10+ years of industrial experience in ASIC design
2. 5+ years or more years of experience in physical design of deep submicron digital ASIC chips
3. Hands on experience in large scale ASIC chip physical design
4. Knowledgeable in all aspects of deep submicron ASIC design flow
5. Successfully gone through several complete product development cycles
6. Demonstrate strong leadership and work well with cross-functional teams
7. Good listening, writing and speaking English
8. Good communication skills, strong interpersonal skills and the flexibility
9. Dedicated, hard working and good team player
10. Familiar with Back-End (physical design) EDA tools
11. Familiar with Front-End EDA tools is a plus
12. Familiar with Unix/Linux environment and good at scripts
Position: SMTS/MTS Design Engineer - DFT
Job Description:
Qualified candidate will perform some or all functions below:
1. Participate in SOC full Chip DFT feature and architecture definition
2. Responsible for DFT specification generation and review
3. Implement SOC DFT function including SCAN, Boundary SCAN, MBIST, Analog Macro test logic.
4. Perform verification on all DFT structures
5. Generate DFT related timing constraints and work with PD team for timing closure
6. Generate and verify DFT structural patterns and functional patterns
7. Participate in ATE bring-up and debug the DFT patterns on ATE
8. Design and implement other DFX (debug, characterization, yield etc) logics
Requirements/Qualifications:
- BS in EE & CS. MS preferred, with 4+ years experience.
- Hands on working experience on ASIC DFT design and verification
- Familiar with entire ASIC design flow
- Experience with micro processor design a big plus
- Should have strong problem solving skills
- Good English hearing, speaking, reading and writing capabilities
- Good communication skills
Job Title: Senior Software Development Engineer
Windows/Linux Graphic Base Driver
ROLE & RESPOSIBILITIES
- Work as part of the global SCBU SW engineering team to design and maintain the graphics device driver
- Resolve problem reports related to graphics device driver including troubleshooting, debugging, & defect correction
- Specify, design and implement software stack for new ASIC or per customer requirement
- Coordinate closely with peers at both Asia and North America to ensure timely and effective communication of all assigned work activities.
- Responsible for the Diagnostic and verification for HW features of new ASIC
DESIRED EXPERIENCE:
- Experience in multi-threaded programming in a x86 or ARM architecture in both kernel & user modes.
- Object-oriented design & programming
- C/C++ programming
- Experience with Windows or Linux kernel driver programming on either x86 or ARM system
- Experience with software debugging and related tool such as WinDbg or gdb in an x86 architecture in both kernel & user modes is a plus
- Min. 3 years direct experience in Windows or Linux graphics driver development is preferred
- Experience in Low-level programming of hardware devices is preferred
- Experience with graphic or display technologies (DisplayPort, HDMI, Stereo 3D display, wireless display, etc.) is a plus
DESIRED KNOWLEDGE, SKILLS & CHARACTERISTICS
- In depth understanding of PC or embedded system architecture
- In depth understanding of Operating System architecture
- Good software debugging logic and hands on knowledge
- Good verbal and written communication skill
- Excellent multi-tasking and prioritization skill
- Good team works
- Self motivated, strong initiative, can work under moderate to minimal supervision
EDUCATION
- BA/BS degree with strong academic background or equivalent experience (higher level degree a plus) in Computer Science, Electrical Engineering, Software Engineering. MS or PHD is a plus.
Title: DB & Application Specialist
SCTA Application Specialist/Developer:
o Maintain existing web and console applications (Silverlight, aspx & perl)
o Develop new applications to manage supply planning, including factory planning, Indices & Yield management & inventory targets for Supply Chain and other cross functional areas of operations
o Assist with transition of AMD MRP to SAP bases solution of next 3-5 years
o Provide regional support for existing applications
Business Experience/Education:
- Preferred experience in semi-conductor companies
- 2-4 Years Development experience for Business applications
- Degree in MIS/Computer Science/Engineering
- Experience deploying MRP software (ie. SAP).
.NET Developer Requirements
- Minimum 2 years of experience in C# and ASP.NET development (.NET 3.5 / 4.0)
- Minimum 2 years of experience in HTML, CSS, JavaScript and JQuery
- Minimum 2 years of experience in WCF and Web Services (Must be very fluent)
- Minimum 2 years of experience in IIS management
- Familiarity with all stages of SDLC (System Development Life Cycle)
- Ability to create functional specifications as needed
- Ability to create functional, load and integration tests as needed
- Excellent understanding of ADO.NET and other data access layers (Entity framework or NHibernate)
- Excellent understanding of SOAP, RESTful services, XML, XSL, and serialization
- Familiarity with SOA concepts
- Familiarity with security models
- Familiarity with Microsoft's Team Foundation Server (TFS)
- Sound knowledge of LINQ to objects and LINQ to SQL
- Minimum 3 years of experience writing complicated SQL joins, Stored Procedures and Views.
- Must be able to communicate very well
Other technical requirements:
- Experience with a reporting engine (Tableau, SSRS)
- Database management (User management, Backups, SQL Profiler, etc…)
APU DV positions with CPU design/DV
AMD’s APU Design/Verification team is looking for highly motivated Verification Engineers to work on next generation SOC APU ASIC design.
Responsibilities Include:
- Verification of Microprocessor SOC Design
- Develop and execute test plans for system level functional features related to Power Management/ Coherency / Security /…etc.
- Participate in testbench development in C/C++/OVM/SV, directed/random stimulus generation and debug.
- Participate in the execution/deployment of new methodologies for improving functional verification of design.
Position requires
- Master in EE or CS;
- Good understanding on the verification flows, EDA tools;
- Good knowledge of computer architecture, X86 assembly programming;
- Verification background in large scale SoC/ASIC is preferred;
- Experience with HDL, Perl, C/C++, OVM is a plus;
- Good command of English language skills (oral and written) ;
- Good communication & inter-personal skills and the ability and desire to work as a team;
Section Manager
Experience
o A minimum of B.Sc. in Computer Science or equivalent. Preferably an advanced Computer Science or Engineering degree (M.Sc. or Ph.D.)
o 8+ years of progressive management experience in a in a large, fast paced software environment
o Experience with resource management.
o Proven mentoring and coaching abilities
o Experience with PC, graphics industry and OEM/ODM models
o Strong knowledge of sound software development processes
o Solid understanding of the Windows graphics environment
o Must be a team player, problem solver and have a “can do” attitude
o Strong leadership and communication skills (English and Mandarin, both written and verbal) are key
o Must work well under pressure and have the ability to multi task effectively
Skills/Competencies
- Build world class teams
- Drives a performance culture
- Results focused
- Horizontal management
- Continuous improvement
(MTS DE)
Requirements:
The candidate is preferred to be MSEE with minimum of 6 years, or BSEE with minimum of 8 years experience in digital ASIC/SOC design engineering.
It is a must that the candidate has one or more of the following experience/knowledge, such as X86/ARM/8051 architecture, AMBA(AXI/AHB/APB) bus, USB(3.0/2.0/1.1; SSIC/HSIC/host/device/OTG) system, NAND Flash host controller/BCH/double-data-rate interface, Universal Flash Storage, PCI-E/PCI bus, low power design, clock generation and control, SD/eMMC host controller, SATA/SAS, Legacy IPs (SPI/SMBUS/ACPI/LPC/GPIO), General connectivity IPs (I2S/I2C/UART), Ethernet, JTAG, etc.
The candidate is expected to exhibit good verbal and written communication skills in both Chinese and English, specialized knowledge plus broad technical knowledge that facilitates integrative thinking, , driving execution of quality and timely result, capability to solve complex, novel and no-recurring problems and decision-making on critical technical areas
Responsibility:
The successful candidate will work with team members and apply his/her design techniques to work on different phases of complex logic design for ASIC/SOC project. The role will include technical leading on the following tasks from time to time: specification, top level SOC design tasks, HDL coding, etc.
之前内推的都是DE和DV 现在有些新的职位，有兴趣的多关注
北京职位已满
内推 有兴趣的发邮件到zzxgxcdma@163.com
地点：上海
title:
3.Front-end ASIC design CAD engineer
4.Windows 2D/3D graphics driver Senior/MTS/section manager
5.MTS/SMTS of Physical Design
6.Sr. Physical Design Engineer
7.MTS DV Engineer (CPU background)
8.MTS DV Engineer (SoC Emulation DV)
9.MTS/SMTS of DFT
10. Sr. Windows/Linux Graphic Base Driver Engineer
地点:北京
title:
地点:苏州
title:
DB & Application Specialist
下面是部分JD：
Sr. Fro-end ASIC Design CAD engineer
Position Summary
? Participate in the design and implementation of the leading edge, front-end ASIC design flow
? Participate in the research of Design Methodology to improve automation and productivity to produce AMD's new high-quality cutting-edge APU and GPU products
? Technical support and programming
? Interface with EDA vendors on technology
Essential Requirements/Qualifications:
1. Major in EE, CS or related, Master Degree with 3+ years or Bachelor with 5+ years working experience
2. Experience in Front-end digital design and VerilogHDL is required
3. Good programming skill with one or more languages (e.g. Tcl, Perl, python, c/c++, etc.) in Unix/Linux and a strong desire to automate flow
4. Familiar with SRAM design and behaviour is a plus
5. Familiar with one or more ASIC flows (logic synthesis, STA etc.) and usage of related EDA tools is a plus
6. Good written and spoken English
7. Good communication skills and be able to work both independently and in a team
Windows 2D/3D graphics driver Senior/MTS engineer
DESCRIPTION OF DUTIES IN ADDITION TO THOSE IN JOB DESCRIPTION:
- Develop and Maintain the AMD GPU DirectX Driver.
- Work with HW design team to tune DirectX Driver performance.
PREFERRED EXPERIENCE:
- Master/Ph.D Degree of Computer Science, Mathematics or Electronic Engineering.
- 3+ years experience working in Graphics Driver under Microsoft Windows.
- 5+ years experience of C/C++ programming.
- Knowledge of DirectX application developing under Microsoft Windows.
- Knowledge of Computer Graphics.
- Knowledge of x86 assembler language and x86/x64 CPU instructions.
- Knowledge of PC architecture.
Physical Design Engineer
这个JD是SMTS的 SR MTS的经验年限要求2+ 5+左右
Job Description:
Work with global Front-End design team and physical design team for large scale ASIC chip physical implementation. Focus on physical design of deep sub-micron GPU chips including block level (full chip) floor planning, timing closure, place&route, physical verification etc. The individual is expected to be an expert in multiple aspects in PD areas and provide technically leadership to the engineering team. The individual is also expected to be accountable for project delivery.
Job Requirement:
1. MSEE with 8+ years or Bachelor with 10+ years of industrial experience in ASIC design
2. 5+ years or more years of experience in physical design of deep submicron digital ASIC chips
3. Hands on experience in large scale ASIC chip physical design
4. Knowledgeable in all aspects of deep submicron ASIC design flow
5. Successfully gone through several complete product development cycles
6. Demonstrate strong leadership and work well with cross-functional teams
7. Good listening, writing and speaking English
8. Good communication skills, strong interpersonal skills and the flexibility
9. Dedicated, hard working and good team player
10. Familiar with Back-End (physical design) EDA tools
11. Familiar with Front-End EDA tools is a plus
12. Familiar with Unix/Linux environment and good at scripts
Position: SMTS/MTS Design Engineer - DFT
Job Description:
Qualified candidate will perform some or all functions below:
1. Participate in SOC full Chip DFT feature and architecture definition
2. Responsible for DFT specification generation and review
3. Implement SOC DFT function including SCAN, Boundary SCAN, MBIST, Analog Macro test logic.
4. Perform verification on all DFT structures
5. Generate DFT related timing constraints and work with PD team for timing closure
6. Generate and verify DFT structural patterns and functional patterns
7. Participate in ATE bring-up and debug the DFT patterns on ATE
8. Design and implement other DFX (debug, characterization, yield etc) logics
Requirements/Qualifications:
- BS in EE & CS. MS preferred, with 4+ years experience.
- Hands on working experience on ASIC DFT design and verification
- Familiar with entire ASIC design flow
- Experience with micro processor design a big plus
- Should have strong problem solving skills
- Good English hearing, speaking, reading and writing capabilities
- Good communication skills
Job Title: Senior Software Development Engineer
Windows/Linux Graphic Base Driver
ROLE & RESPOSIBILITIES
- Work as part of the global SCBU SW engineering team to design and maintain the graphics device driver
- Resolve problem reports related to graphics device driver including troubleshooting, debugging, & defect correction
- Specify, design and implement software stack for new ASIC or per customer requirement
- Coordinate closely with peers at both Asia and North America to ensure timely and effective communication of all assigned work activities.
- Responsible for the Diagnostic and verification for HW features of new ASIC
DESIRED EXPERIENCE:
- Experience in multi-threaded programming in a x86 or ARM architecture in both kernel & user modes.
- Object-oriented design & programming
- C/C++ programming
- Experience with Windows or Linux kernel driver programming on either x86 or ARM system
- Experience with software debugging and related tool such as WinDbg or gdb in an x86 architecture in both kernel & user modes is a plus
- Min. 3 years direct experience in Windows or Linux graphics driver development is preferred
- Experience in Low-level programming of hardware devices is preferred
- Experience with graphic or display technologies (DisplayPort, HDMI, Stereo 3D display, wireless display, etc.) is a plus
DESIRED KNOWLEDGE, SKILLS & CHARACTERISTICS
- In depth understanding of PC or embedded system architecture
- In depth understanding of Operating System architecture
- Good software debugging logic and hands on knowledge
- Good verbal and written communication skill
- Excellent multi-tasking and prioritization skill
- Good team works
- Self motivated, strong initiative, can work under moderate to minimal supervision
EDUCATION
- BA/BS degree with strong academic background or equivalent experience (higher level degree a plus) in Computer Science, Electrical Engineering, Software Engineering. MS or PHD is a plus.
Title: DB & Application Specialist
SCTA Application Specialist/Developer:
o Maintain existing web and console applications (Silverlight, aspx & perl)
o Develop new applications to manage supply planning, including factory planning, Indices & Yield management & inventory targets for Supply Chain and other cross functional areas of operations
o Assist with transition of AMD MRP to SAP bases solution of next 3-5 years
o Provide regional support for existing applications
Business Experience/Education:
- Preferred experience in semi-conductor companies
- 2-4 Years Development experience for Business applications
- Degree in MIS/Computer Science/Engineering
- Experience deploying MRP software (ie. SAP).
.NET Developer Requirements
- Minimum 2 years of experience in C# and ASP.NET development (.NET 3.5 / 4.0)
- Minimum 2 years of experience in HTML, CSS, JavaScript and JQuery
- Minimum 2 years of experience in WCF and Web Services (Must be very fluent)
- Minimum 2 years of experience in IIS management
- Familiarity with all stages of SDLC (System Development Life Cycle)
- Ability to create functional specifications as needed
- Ability to create functional, load and integration tests as needed
- Excellent understanding of ADO.NET and other data access layers (Entity framework or NHibernate)
- Excellent understanding of SOAP, RESTful services, XML, XSL, and serialization
- Familiarity with SOA concepts
- Familiarity with security models
- Familiarity with Microsoft's Team Foundation Server (TFS)
- Sound knowledge of LINQ to objects and LINQ to SQL
- Minimum 3 years of experience writing complicated SQL joins, Stored Procedures and Views.
- Must be able to communicate very well
Other technical requirements:
- Experience with a reporting engine (Tableau, SSRS)
- Database management (User management, Backups, SQL Profiler, etc…)
APU DV positions with CPU design/DV
AMD’s APU Design/Verification team is looking for highly motivated Verification Engineers to work on next generation SOC APU ASIC design.
Responsibilities Include:
- Verification of Microprocessor SOC Design
- Develop and execute test plans for system level functional features related to Power Management/ Coherency / Security /…etc.
- Participate in testbench development in C/C++/OVM/SV, directed/random stimulus generation and debug.
- Participate in the execution/deployment of new methodologies for improving functional verification of design.
Position requires
- Master in EE or CS;
- Good understanding on the verification flows, EDA tools;
- Good knowledge of computer architecture, X86 assembly programming;
- Verification background in large scale SoC/ASIC is preferred;
- Experience with HDL, Perl, C/C++, OVM is a plus;
- Good command of English language skills (oral and written) ;
- Good communication & inter-personal skills and the ability and desire to work as a team;
Section Manager
Experience
o A minimum of B.Sc. in Computer Science or equivalent. Preferably an advanced Computer Science or Engineering degree (M.Sc. or Ph.D.)
o 8+ years of progressive management experience in a in a large, fast paced software environment
o Experience with resource management.
o Proven mentoring and coaching abilities
o Experience with PC, graphics industry and OEM/ODM models
o Strong knowledge of sound software development processes
o Solid understanding of the Windows graphics environment
o Must be a team player, problem solver and have a “can do” attitude
o Strong leadership and communication skills (English and Mandarin, both written and verbal) are key
o Must work well under pressure and have the ability to multi task effectively
Skills/Competencies
- Build world class teams
- Drives a performance culture
- Results focused
- Horizontal management
- Continuous improvement
(MTS DE)
Requirements:
The candidate is preferred to be MSEE with minimum of 6 years, or BSEE with minimum of 8 years experience in digital ASIC/SOC design engineering.
It is a must that the candidate has one or more of the following experience/knowledge, such as X86/ARM/8051 architecture, AMBA(AXI/AHB/APB) bus, USB(3.0/2.0/1.1; SSIC/HSIC/host/device/OTG) system, NAND Flash host controller/BCH/double-data-rate interface, Universal Flash Storage, PCI-E/PCI bus, low power design, clock generation and control, SD/eMMC host controller, SATA/SAS, Legacy IPs (SPI/SMBUS/ACPI/LPC/GPIO), General connectivity IPs (I2S/I2C/UART), Ethernet, JTAG, etc.
The candidate is expected to exhibit good verbal and written communication skills in both Chinese and English, specialized knowledge plus broad technical knowledge that facilitates integrative thinking, , driving execution of quality and timely result, capability to solve complex, novel and no-recurring problems and decision-making on critical technical areas
Responsibility:
The successful candidate will work with team members and apply his/her design techniques to work on different phases of complex logic design for ASIC/SOC project. The role will include technical leading on the following tasks from time to time: specification, top level SOC design tasks, HDL coding, etc.