AMD内部推荐（上海 ）
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GPU Silicon Validation Arch Design Engineering：
Requirement:
o A minimum of 8+ years experience, 3+ years experience in either pre-silicon or post-silicon design verification and closely interact with HW designers
o Solid understanding for ASIC/SoC design flow and validation process
o Excellent knowledge and experience with pre-silicon and post-silicon verification methodologies and tools, such as SW emulator, simulation, FPGA, benchmark tools, etc.
o Good understanding for at least one ISA SoC architecture, such as X86, ARM, MIPS, etc
o Program management skills
o Good software programming experience for C/C++
o Strong communication skills in both Chinese and English
o Knowledge and experience for 3D graphics is highly desired
GPU Compute Architect (Engineer of Graphics Performance Verification)
More than 5 years’ experience with one of following:
- a) Software: OGL/D3D driver background
- b) 3D/GPU Architecture
- c) IC Design/verification Background
- d) GPU design/verification
- e) 3D Application programming etc.
- f) Compiler Back Ground
- g) Graphics Architecture
- h) GPGPU related jobs
Preferred Experience:
- Master Degree or Above
- 5+ year experience on C\C++
- Plus with experience on GPU Design/Verification
- Plus with experience on Compiler
- Plus with 3+ years’ OpenGL/D3D programming experience
- Plus with 3+ years’ OpenGL/D3D driver experience
- Plus with 1+ years’ Linux/Shell
- Plus with 1+ years’ Perl/Python
- Familiar with Graphics Algorithm/Graphics Pipeline
- Proficient in English read/write/speaking/listening
- Good communication & Team worker
Staff Engineer of GFX Design Verification
Job Description:
o Read and understand graphics specification for new hardware architecture.
o Work with global team to write chip level test plan.
o Based on the test plan to write chip level tests to verify the function of graphics IP core.
o Debug the test to get expected result on C-model.
o Debug to locate issue of the fail on C-model and RTL-model, and push designer to fix.
Requirements:
o Major in EE, CS or Math, Master Degree with 5+ years or Bachelor with 7+ years working experiences
o Strong program/debug ability on c/c++.
o Familiar to graphics algorithm like rendering/shader.
o Familiar to linux env/script is a big plus.
o Strong communication skill and experience of across team/region work
o Good oral and written English capability
MTS ASIC SoC Design Verification
Job Requirements:
The candidate is preferred to be MSEE with minimum of 6 years, or BSEE with minimum of 8 years experience in digital ASIC/SOC design verification.
The candidate must have:
1. Deep understanding on ASIC/SOC design flow
2. Excellent knowledge of design verification methodology, such as VMM or OVM.
3. Solid experiences with simulation model creation and the testbench build
4. Strong RTL coding with Verilog
5. Strong C/C++ software development experiences
6. Be good at scripting language, such as Perl, C shell, Makefile.
It is a must that the candidate has one or more of the following experience/knowledge, such as GPU/X86/ARM/8051 architecture, AMBA(AXI/AHB/APB) bus, USB(3.0/2.0/1.1; HSIC/host/device/OTG) system, NAND Flash host controller/BCH/double-data-rate interface, PCI-E/PCI bus, low power design, clock generation and control, SD/eMMC host controller, SATA/SAS, Legacy IPs
(SPI/SMBUS/ACPI/LPC/GPIO), General connectivity IPs (I2S/I2C/UART), Ethernet, JTAG, etc.
The candidate is expected to exhibit good verbal and written communication skills in both Chinese and English, specialized knowledge plus broad technical knowledge that facilitates integrative thinking, , driving execution of quality and timely result, capability to solve complex, novel and no-recurring problems and decision-making on critical technical areas
Senior Design Engineer of GPU IP
Job Description: Responsibility:
o Develop micro-architecture for GPU blocks based on architectural requirement.
o Develop RTL code for GPU blocks in Verilog HDL and make sure functional correct and reusable for different configuration.
o Synthesis and deliver netlist that meeting timing, area and power requirement. Help PD on the floorplanning and close timing.
Requirement:
o Familiar with Verilog RTL design and has experience of digital ASIC project.
o Familiar with front-end EDA tools and flows.
o Familiar with C/C++ programming and unix/linux and scripts (tcl, perl etc.)
o Fluent English on talking, presentation and writing documents.
o Work is performed with limited supervision. Strong sense of task scheduling and deliver on time as predetermined milestones committed to manager.
o Possesses specialized knowledge of Computer architecture and computer arithmetic (a plus)
GPU Silicon Validation Arch Design Engineering：
Requirement:
o A minimum of 8+ years experience, 3+ years experience in either pre-silicon or post-silicon design verification and closely interact with HW designers
o Solid understanding for ASIC/SoC design flow and validation process
o Excellent knowledge and experience with pre-silicon and post-silicon verification methodologies and tools, such as SW emulator, simulation, FPGA, benchmark tools, etc.
o Good understanding for at least one ISA SoC architecture, such as X86, ARM, MIPS, etc
o Program management skills
o Good software programming experience for C/C++
o Strong communication skills in both Chinese and English
o Knowledge and experience for 3D graphics is highly desired
GPU Compute Architect (Engineer of Graphics Performance Verification)
More than 5 years’ experience with one of following:
- a) Software: OGL/D3D driver background
- b) 3D/GPU Architecture
- c) IC Design/verification Background
- d) GPU design/verification
- e) 3D Application programming etc.
- f) Compiler Back Ground
- g) Graphics Architecture
- h) GPGPU related jobs
Preferred Experience:
- Master Degree or Above
- 5+ year experience on C\C++
- Plus with experience on GPU Design/Verification
- Plus with experience on Compiler
- Plus with 3+ years’ OpenGL/D3D programming experience
- Plus with 3+ years’ OpenGL/D3D driver experience
- Plus with 1+ years’ Linux/Shell
- Plus with 1+ years’ Perl/Python
- Familiar with Graphics Algorithm/Graphics Pipeline
- Proficient in English read/write/speaking/listening
- Good communication & Team worker
Staff Engineer of GFX Design Verification
Job Description:
o Read and understand graphics specification for new hardware architecture.
o Work with global team to write chip level test plan.
o Based on the test plan to write chip level tests to verify the function of graphics IP core.
o Debug the test to get expected result on C-model.
o Debug to locate issue of the fail on C-model and RTL-model, and push designer to fix.
Requirements:
o Major in EE, CS or Math, Master Degree with 5+ years or Bachelor with 7+ years working experiences
o Strong program/debug ability on c/c++.
o Familiar to graphics algorithm like rendering/shader.
o Familiar to linux env/script is a big plus.
o Strong communication skill and experience of across team/region work
o Good oral and written English capability
MTS ASIC SoC Design Verification
Job Requirements:
The candidate is preferred to be MSEE with minimum of 6 years, or BSEE with minimum of 8 years experience in digital ASIC/SOC design verification.
The candidate must have:
1. Deep understanding on ASIC/SOC design flow
2. Excellent knowledge of design verification methodology, such as VMM or OVM.
3. Solid experiences with simulation model creation and the testbench build
4. Strong RTL coding with Verilog
5. Strong C/C++ software development experiences
6. Be good at scripting language, such as Perl, C shell, Makefile.
It is a must that the candidate has one or more of the following experience/knowledge, such as GPU/X86/ARM/8051 architecture, AMBA(AXI/AHB/APB) bus, USB(3.0/2.0/1.1; HSIC/host/device/OTG) system, NAND Flash host controller/BCH/double-data-rate interface, PCI-E/PCI bus, low power design, clock generation and control, SD/eMMC host controller, SATA/SAS, Legacy IPs
(SPI/SMBUS/ACPI/LPC/GPIO), General connectivity IPs (I2S/I2C/UART), Ethernet, JTAG, etc.
The candidate is expected to exhibit good verbal and written communication skills in both Chinese and English, specialized knowledge plus broad technical knowledge that facilitates integrative thinking, , driving execution of quality and timely result, capability to solve complex, novel and no-recurring problems and decision-making on critical technical areas
Senior Design Engineer of GPU IP
Job Description: Responsibility:
o Develop micro-architecture for GPU blocks based on architectural requirement.
o Develop RTL code for GPU blocks in Verilog HDL and make sure functional correct and reusable for different configuration.
o Synthesis and deliver netlist that meeting timing, area and power requirement. Help PD on the floorplanning and close timing.
Requirement:
o Familiar with Verilog RTL design and has experience of digital ASIC project.
o Familiar with front-end EDA tools and flows.
o Familiar with C/C++ programming and unix/linux and scripts (tcl, perl etc.)
o Fluent English on talking, presentation and writing documents.
o Work is performed with limited supervision. Strong sense of task scheduling and deliver on time as predetermined milestones committed to manager.
o Possesses specialized knowledge of Computer architecture and computer arithmetic (a plus)