猎头代招美半导体公司
时间：12-12
整理：3721RD
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目前还有1个headcount，有兴趣的同学尽快发简历给我吧，谢谢:-)
简历请发送到headhunter_000@163.com,座机电话：010-六七1久1五七3
工作地点北京。
responsible for the design of our next generation compression products and SOCs to join our dynamic team in Beijing. Tasks include micro-architecture, RTL design, synthesis, timing analysis and DFT.
The candidate must work with architecture teams to develop efficient micro-architecture for a module. In addition, the candidate needs to contribute heavily to full chip integration and flow development to minimize design effort and time.
Primary Responsibilities:
• IP design, maintain and integration. Support physical design, board development and product engineering teams through tape-out, silicon qualification and high volume production
Qualifications:
• BS/MS EE
• 1+ years in ASIC design experience
• Experienced on SoC
• Experienced in chip level integration
• Experienced in basic aspects of ASIC flow – synthesis, timing
• Family with scripting language.
• Good written and verbal communication skills
• Ability to communicate well in English, verbal and written
• Lab/bring-up experience is a plus
• FPGA experience is a plus
• MIPS, Video, Codec and prior design experience is a plus.
简历请发送到headhunter_000@163.com,座机电话：010-六七1久1五七3
工作地点北京。
responsible for the design of our next generation compression products and SOCs to join our dynamic team in Beijing. Tasks include micro-architecture, RTL design, synthesis, timing analysis and DFT.
The candidate must work with architecture teams to develop efficient micro-architecture for a module. In addition, the candidate needs to contribute heavily to full chip integration and flow development to minimize design effort and time.
Primary Responsibilities:
• IP design, maintain and integration. Support physical design, board development and product engineering teams through tape-out, silicon qualification and high volume production
Qualifications:
• BS/MS EE
• 1+ years in ASIC design experience
• Experienced on SoC
• Experienced in chip level integration
• Experienced in basic aspects of ASIC flow – synthesis, timing
• Family with scripting language.
• Good written and verbal communication skills
• Ability to communicate well in English, verbal and written
• Lab/bring-up experience is a plus
• FPGA experience is a plus
• MIPS, Video, Codec and prior design experience is a plus.