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1. The influence of the layout on the ESD performance of HV-LDMOS
http://ieeexplore.ieee.org/search/freesrchabstract.jsp?tp=&arnumber=5543900&queryText%3Desd+ldmos%26openedRefinements%3D*%26filter%3DAND%28NOT%284283010803%29%29%26searchField%3DSearch+All
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Jian-Hsing Lee; Hung-Der Su; Chien-Ling Chan; Yang, D.; Chen, J.F.; Wu, K.M.;
Technol. Dev. Div., Richtek Technol. Corp., Chubei, Taiwan
This paper appears in: Power Semiconductor Devices & IC's (ISPSD), 2010 22nd International Symposium on
Issue Date : 6-10 June 2010
On page(s): 303 - 306
ISSN : 1943-653X
Print ISBN: 978-1-4244-7718-0
References Cited: 7
INSPEC Accession Number: 11465731
Date of Current Version : 09 八月 2010
ABSTRACT
The root causes of the high voltage (HV) LDMOS (Fig. 2) failed at the low voltage electrostatic-discharge (ESD) zap is found. One is caused by the bulk layout and one is caused by the intrinsic characteristic of the device. From the findings, a new structure is proposed to eliminate the root causes without sacrificing the IV characteristics and dimension of the device.
2. The influence of the layout on the ESD performance of HV-LDMOS
http://ieeexplore.ieee.org/search/freesrchabstract.jsp?tp=&arnumber=4017182&queryText%3Desd+ldmos%26openedRefinements%3D*%26filter%3DAND%28NOT%284283010803%29%29%26searchField%3DSearch+All
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Jian-Hsing Lee; Hung-Der Su; Chien-Ling Chan; Yang, D.; Chen, J.F.; Wu, K.M.;
Technol. Dev. Div., Richtek Technol. Corp., Chubei, Taiwan
This paper appears in: Power Semiconductor Devices & IC's (ISPSD), 2010 22nd International Symposium on
Issue Date : 6-10 June 2010
On page(s): 303 - 306
ISSN : 1943-653X
Print ISBN: 978-1-4244-7718-0
References Cited: 7
INSPEC Accession Number: 11465731
Date of Current Version : 09 八月 2010
ABSTRACT
The root causes of the high voltage (HV) LDMOS (Fig. 2) failed at the low voltage electrostatic-discharge (ESD) zap is found. One is caused by the bulk layout and one is caused by the intrinsic characteristic of the device. From the findings, a new structure is proposed to eliminate the root causes without sacrificing the IV characteristics and dimension of the device.
1. The influence of the layout on the ESD performance of HV-LDMOS
http://ieeexplore.ieee.org/search/freesrchabstract.jsp?tp=&arnumber=5543900&queryText%3Desd+ldmos%26openedRefinements%3D*%26filter%3DAND%28NOT%284283010803%29%29%26searchField%3DSearch+All
Access The Full Text
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Jian-Hsing Lee; Hung-Der Su; Chien-Ling Chan; Yang, D.; Chen, J.F.; Wu, K.M.;
Technol. Dev. Div., Richtek Technol. Corp., Chubei, Taiwan
This paper appears in: Power Semiconductor Devices & IC's (ISPSD), 2010 22nd International Symposium on
Issue Date : 6-10 June 2010
On page(s): 303 - 306
ISSN : 1943-653X
Print ISBN: 978-1-4244-7718-0
References Cited: 7
INSPEC Accession Number: 11465731
Date of Current Version : 09 八月 2010
ABSTRACT
The root causes of the high voltage (HV) LDMOS (Fig. 2) failed at the low voltage electrostatic-discharge (ESD) zap is found. One is caused by the bulk layout and one is caused by the intrinsic characteristic of the device. From the findings, a new structure is proposed to eliminate the root causes without sacrificing the IV characteristics and dimension of the device.
2. The influence of the layout on the ESD performance of HV-LDMOS
http://ieeexplore.ieee.org/search/freesrchabstract.jsp?tp=&arnumber=4017182&queryText%3Desd+ldmos%26openedRefinements%3D*%26filter%3DAND%28NOT%284283010803%29%29%26searchField%3DSearch+All
Access The Full Text
SIGN IN:Full text access may be available with your subscription
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Jian-Hsing Lee; Hung-Der Su; Chien-Ling Chan; Yang, D.; Chen, J.F.; Wu, K.M.;
Technol. Dev. Div., Richtek Technol. Corp., Chubei, Taiwan
This paper appears in: Power Semiconductor Devices & IC's (ISPSD), 2010 22nd International Symposium on
Issue Date : 6-10 June 2010
On page(s): 303 - 306
ISSN : 1943-653X
Print ISBN: 978-1-4244-7718-0
References Cited: 7
INSPEC Accession Number: 11465731
Date of Current Version : 09 八月 2010
ABSTRACT
The root causes of the high voltage (HV) LDMOS (Fig. 2) failed at the low voltage electrostatic-discharge (ESD) zap is found. One is caused by the bulk layout and one is caused by the intrinsic characteristic of the device. From the findings, a new structure is proposed to eliminate the root causes without sacrificing the IV characteristics and dimension of the device.
Done.
1和2不是一样么？
fluence_of_the_layout_on_the_ESD_performance_of_HV-LDMOS.pdf