CMOS High-Speed I/O - Background, Circuits, and
时间：12-12
整理：3721RD
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Speaker:
Tszshing CHEUNG,
Fujitsu Laboratories Limited,
IEEE A-SSCC TPC Committee,
IEEE SSCC Lecturer,
IEEE Committee Member
Seminar Host: Department of Microelectronics, Peking Univ.
Time: 2:00pm~5:00pm, Nov 10
Venue: Science Building 2, Room 2135, Peking Univ.
Chair: Prof Weixin Gai, Peking Univ.
Abstracts
Part 1: The Latest Trend of Low Power High-Speed CMOS I/O Technology for Photonic Network (1 hour 15 min.)
The latest trend of high-speed input/output (I/O) interface technology for the next generation high-efficiency network will be introduced.
The development of high-speed I/O technology contributes to lower power and lower cost system in photonic network. In this part, the high-speed I/O trends will be introduced, and the CMOS process technology and circuit design technique which support it, will be discussed. Finally, the issues and future outlooks (including the Latest Trend of Low Power High-Speed CMOS I/O Technology) will be described.
On the other hand, technology of high speed I/O components is shifting to real 40Gbps applications, for both electrical interfaces and photonic networks. Should all the components be built with CMOS? Should the interfaces be implemented with serial or parallel ports?
Part 2: High Speed CMOS Interface and Related Equalizing Techniques (1 hour 15 min.)
Background of Data Communication (Datacom) Systems will be addressed. High speed I/Os (also called High Speed Interface, Interconnect Circuits) are essential part for Computers and Data Communication Servers. At the beginning, trends in IC bandwidth and circuit solution for multi-data-rate, multi-port I/O will be introduced. A CMOS 10Gbps transceiver will be used as example for discussion.
Due to channel attenuation, Inter-symbol interference (ISI) and system structure, there is often distortion in transmitted data signal. In various conditions, equalization circuits become necessary for Data Communication systems. Some examples of typical equalizers, including high speed pre-emphasized transmitter, equalizer, and 10-20Gbps transmitter and receiver, will be introduced. Concepts and effects of pre-emphasis transmitter (Tx), analog receiver with equalization, Partial Response Detection circuit, and decision-feedback equalization (DFE), will be introduced.
Tszshing CHEUNG,
Fujitsu Laboratories Limited,
IEEE A-SSCC TPC Committee,
IEEE SSCC Lecturer,
IEEE Committee Member
Seminar Host: Department of Microelectronics, Peking Univ.
Time: 2:00pm~5:00pm, Nov 10
Venue: Science Building 2, Room 2135, Peking Univ.
Chair: Prof Weixin Gai, Peking Univ.
Abstracts
Part 1: The Latest Trend of Low Power High-Speed CMOS I/O Technology for Photonic Network (1 hour 15 min.)
The latest trend of high-speed input/output (I/O) interface technology for the next generation high-efficiency network will be introduced.
The development of high-speed I/O technology contributes to lower power and lower cost system in photonic network. In this part, the high-speed I/O trends will be introduced, and the CMOS process technology and circuit design technique which support it, will be discussed. Finally, the issues and future outlooks (including the Latest Trend of Low Power High-Speed CMOS I/O Technology) will be described.
On the other hand, technology of high speed I/O components is shifting to real 40Gbps applications, for both electrical interfaces and photonic networks. Should all the components be built with CMOS? Should the interfaces be implemented with serial or parallel ports?
Part 2: High Speed CMOS Interface and Related Equalizing Techniques (1 hour 15 min.)
Background of Data Communication (Datacom) Systems will be addressed. High speed I/Os (also called High Speed Interface, Interconnect Circuits) are essential part for Computers and Data Communication Servers. At the beginning, trends in IC bandwidth and circuit solution for multi-data-rate, multi-port I/O will be introduced. A CMOS 10Gbps transceiver will be used as example for discussion.
Due to channel attenuation, Inter-symbol interference (ISI) and system structure, there is often distortion in transmitted data signal. In various conditions, equalization circuits become necessary for Data Communication systems. Some examples of typical equalizers, including high speed pre-emphasized transmitter, equalizer, and 10-20Gbps transmitter and receiver, will be introduced. Concepts and effects of pre-emphasis transmitter (Tx), analog receiver with equalization, Partial Response Detection circuit, and decision-feedback equalization (DFE), will be introduced.
可惜不在北京，哪位能将PPT整过来Share一下？