如何用Verilog对SRAM建模？

rt，
要用Verilog给SRAM六管单元建立仿真模型，不要求综合的。
本质上讲就是2个反相器首尾相接，
但是我试过了
assign a = ~b;
assign b = ~a;
这种描述，显然不行-_-
有虾米好办法来给SRAM建模吗？
附图如下：

给你搜到这个，但是貌似你要的不是这样的？
//SRAM Model
module sram(CSB,WRB,ABUS,DATABUS);
  input CSB;             // active low chip select
  input WRB;             // active low write control
  input [11:0] ABUS;     // 12-bit address bus
  inout [7:0] DATABUS;   // 8-bit data bus
                 //** internal signals
  reg  [7:0] DATABUS_driver;
  wire [7:0] DATABUS = DATABUS_driver;
  reg [7:0] ram[0:4095];            // memory cells
  integer i;
  initial     //initialize all RAM cells to 0 at startup
    begin
    DATABUS_driver = 8'bzzzzzzzz;
    for (i=0; i < 4095; i = i + 1)
       ram[i] = 0;
    end
  always @(CSB or WRB or ABUS)
    begin
      if (CSB == 1'b0)
        begin
        if (WRB == 1'b0) //Start: latch Data on rising edge of CSB or WRB
          begin
          DATABUS_driver <= #10 8'bzzzzzzzz;
          @(posedge CSB or posedge WRB);
          $display($time," Writing %m ABUS=%b DATA=%b",ABUS,DATABUS);
          ram[ABUS] = DATABUS;
          end
        if (WRB == 1'b1) //Reading from sram (data becomes valid after 10ns)
          begin
          #10 DATABUS_driver =  ram[ABUS];
          $display($time," Reading %m ABUS=%b DATA=%b",ABUS,DATABUS_driver);
          end
        end
      else //sram unselected, stop driving bus after 10ns
        begin
        DATABUS_driver <=  #10 8'bzzzzzzzz;
        end
    end
endmodule
.63
.63

建议找个spice model
然后直接转成vlog model
用关键字pmos，nmos和buf