verilog HDL 里pullup.pulldown怎么用的？
时间：10-02
整理：3721RD
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假如 module top;
wire a;
pullup x1(a);
endmodule
这时a的值不应该是1嘛?为什么是X?
我不会用 = =
仿真的输出结果为：
wire a;
pullup x1(a);
endmodule
这时a的值不应该是1嘛?为什么是X?
我不会用 = =
呃，所谓上下拉应该是对当前无驱动的线才会有作用，若有驱动应该按照驱动信号来决定！
也就是‘Z’可以变成‘1’或‘0’，而不是‘0’能变‘1’（‘1’变‘0’），否则就跟你设计想法不一样了。
至于为什么会是‘X’，我觉得是你的设计问题，看一下是多驱动问题还是X态传播问题。
= = 我懂了，呵呵。 其实是我 display查看时的时序有问题，所以看不出上拉的1..
学习了，呵呵
仿真看看应该是1
小编，我也遇到同样的问题，请问你是怎么怎么解决的啊?
- `timescale 1ns/1ps
- module test();
- reg a;
- reg d;
- wire b;
- wire c;
- wire e;
- reg clk;
- always #10 clk = ~clk;
- initial begin
- clk =1'b0;
- d = 1'bx;
- #100;
- a = 1'b1;
- #100;
- a = 1'b0;
- #100;
- d = 1'bz;
- #100;
- $finish;
- end
- pulldown(b);
- pulldown(c);
- pulldown(e);
- assign b = a;
- assign e = d;
- always@(posedge clk) begin
- $display("@%0t a = %b b = %b c= %b d = %b e = %b ",$realtime,a,b,c,d,e);
- end
- endmodule
仿真的输出结果为：
- @10000 a = x b = x c= 0 d = x e = x
- @30000 a = x b = x c= 0 d = x e = x
- @50000 a = x b = x c= 0 d = x e = x
- @70000 a = x b = x c= 0 d = x e = x
- @90000 a = x b = x c= 0 d = x e = x
- @110000 a = 1 b = 1 c= 0 d = x e = x
- @130000 a = 1 b = 1 c= 0 d = x e = x
- @150000 a = 1 b = 1 c= 0 d = x e = x
- @170000 a = 1 b = 1 c= 0 d = x e = x
- @190000 a = 1 b = 1 c= 0 d = x e = x
- @210000 a = 0 b = 0 c= 0 d = x e = x
- @230000 a = 0 b = 0 c= 0 d = x e = x
- @250000 a = 0 b = 0 c= 0 d = x e = x
- @270000 a = 0 b = 0 c= 0 d = x e = x
- @290000 a = 0 b = 0 c= 0 d = x e = x
- @310000 a = 0 b = 0 c= 0 d = z e = 0
- @330000 a = 0 b = 0 c= 0 d = z e = 0
- @350000 a = 0 b = 0 c= 0 d = z e = 0
- @370000 a = 0 b = 0 c= 0 d = z e = 0
- @390000 a = 0 b = 0 c= 0 d = z e = 0
看看
看看，学习下
看看，学习下