viviado仿真
时间：10-02
整理：3721RD
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[USF-XSim 62] 'compile' step failed with error(s). Please check the Tcl console output or 'E:/ADC_DAC_TEST_948/signal_process/signal_cic_fir/signal_cic_fir.sim/sim_1/behav/xvlog.log' file for more information.
[Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
请问是什么原因
[Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
请问是什么原因
查看TCL console里面的内容或者在log文件里看看报错的原因