FPGA管脚预综合的问题
时间：10-02
整理：3721RD
点击：
ise在implement design时出现
A clock IOB / BUFGCTRL clock component pair have been found
that are not placed at an optimal clock IOB / BUFGCTRL site pair. The clock
IOB component <rclk> is placed at site <A11>. The corresponding BUFGCTRL
component <rclk_BUFGP/BUFG> is placed at site <BUFGCTRL_X0Y0>. The clock IO
can use the fast path between the IOB and the Clock Buffer if the IOB is
placed on a Clock Capable IOB site that has dedicated fast path to BUFGCTRL
sites in its half of the device (TOP or BOTTOM). You may want to analyze why
this problem exists and correct it. If this sub optimal condition is
acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint
in the .ucf file to demote this message to a WARNING and allow your design to
continue. However, the use of this override is highly discouraged as it may
lead to very poor timing results. It is recommended that this error condition
ERRORlace:1398 - A clock IOB / BUFGCTRL clock component pair have been found
that are not placed at an optimal clock IOB / BUFGCTRL site pair. The clock
IOB component <wclk> is placed at site <B11>. The corresponding BUFGCTRL
component <wclk_BUFGP/BUFG> is placed at site <BUFGCTRL_X0Y1>. The clock IO
can use the fast path between the IOB and the Clock Buffer if the IOB is
placed on a Clock Capable IOB site that has dedicated fast path to BUFGCTRL
sites in its half of the device (TOP or BOTTOM). You may want to analyze why
this problem exists and correct it. If this sub optimal condition is
acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint
in the .ucf file to demote this message to a WARNING and allow your design to
continue. However, the use of this override is highly discouraged as it may
lead to very poor timing results. It is recommended that this error condition
be corrected in the design. A list of all the COMP.PINs used in this clock
placement rule is listed below. These examples can be used directly in the
.ucf file to override this clock rule.
< NET "wclk" CLOCK_DEDICATED_ROUTE = FALSE; >
这样的error，请教大神如何解决及为什么会出现这样的错误
A clock IOB / BUFGCTRL clock component pair have been found
that are not placed at an optimal clock IOB / BUFGCTRL site pair. The clock
IOB component <rclk> is placed at site <A11>. The corresponding BUFGCTRL
component <rclk_BUFGP/BUFG> is placed at site <BUFGCTRL_X0Y0>. The clock IO
can use the fast path between the IOB and the Clock Buffer if the IOB is
placed on a Clock Capable IOB site that has dedicated fast path to BUFGCTRL
sites in its half of the device (TOP or BOTTOM). You may want to analyze why
this problem exists and correct it. If this sub optimal condition is
acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint
in the .ucf file to demote this message to a WARNING and allow your design to
continue. However, the use of this override is highly discouraged as it may
lead to very poor timing results. It is recommended that this error condition
ERRORlace:1398 - A clock IOB / BUFGCTRL clock component pair have been found
that are not placed at an optimal clock IOB / BUFGCTRL site pair. The clock
IOB component <wclk> is placed at site <B11>. The corresponding BUFGCTRL
component <wclk_BUFGP/BUFG> is placed at site <BUFGCTRL_X0Y1>. The clock IO
can use the fast path between the IOB and the Clock Buffer if the IOB is
placed on a Clock Capable IOB site that has dedicated fast path to BUFGCTRL
sites in its half of the device (TOP or BOTTOM). You may want to analyze why
this problem exists and correct it. If this sub optimal condition is
acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint
in the .ucf file to demote this message to a WARNING and allow your design to
continue. However, the use of this override is highly discouraged as it may
lead to very poor timing results. It is recommended that this error condition
be corrected in the design. A list of all the COMP.PINs used in this clock
placement rule is listed below. These examples can be used directly in the
.ucf file to override this clock rule.
< NET "wclk" CLOCK_DEDICATED_ROUTE = FALSE; >
这样的error，请教大神如何解决及为什么会出现这样的错误
时钟信号输入应接特定的管脚而不是普通IO
好的，谢谢，那么rst信号有要求么