小白首次搭建环境
xilinx ISE
xilinx vivado
modelsim
grtools
资料：grlib-gpl-1.4.1-b4156.tar.gz
板子：xilinx virtex-7
希望能有好人教教我。
求教求教。希望好心人帮忙
帖子可别沉啊，很着急啊，真心请能帮忙的人帮我一把吧。
你用的ISE还是VIVADO?
我用的是ISE，但是师兄跟我说让我安装cygwin，然后用一系列命令来执行调用各种工具
cygwin 不懂
我也是刚学习ISE，正在摸索阶段
cygwin就是在windows下装的一个linux环境，方便在win下调试linux的软件，你可以把它当成一个虚拟机，但又不完全是
握手握手，同是小白
This leon3 design is tailored to the Xilinx Virtex-7 VC707 board
http://www.xilinx.com/vc707
Note: This design requires that the GRLIB_SIMULATOR variable is
correctly set. Please refer to the documentation in doc/grlib.pdf for
additional information.
Note: The Vivado flow and parts of this design are still
experimental. Currently the design configuration should be left as-is.
Note: You must have Vivado 2014.4.1 in your path for the make targets to work.
The XILINX_VIVADO variable must be exported for the mig_7series target
to work correctly: export XILINX_VIVADO
Simulation and synthesis
------------------------
The design uses the Xilinx MIG memory interface with an AHB-2.0
interface and Xilinx SGMII PHY Interface. The MIG or the SGMII PHY
source code cannot be distributed due to the prohibitive Xilinx
license, so the MIG and/or the SGMII must be re-generated with
Vivado before simulation and synthesis can be done.
Xilinx MIG and SGMII interface will automatically be generated when
Vivado is launched
To simulate using XSIM and run systest.c on the Leon design using the memory
controller from Xilinx use the make targets:
make soft
make vivado-launch
To simulate using Modelsim/Aldec and run systest.c on the Leon design using
the memory controller from Xilinx use the make targets:
make map_xilinx_7series_lib
make sim
make mig_7series
make sgmii_7series
make sim-launch
To simulate using the Aldec Riviera WS flow use the following make targets:
make riviera_ws # creates riviera workspace
make map_xilinx_7series_lib # compiles and maps xilinx sim libs
make mig_7series # generates MIG IP and adds to riviera project
make sgmii_7series # same for SGMII adapter
make riviera # compile full project
make riviera-launch # launch simulation
To synthesize the design, do
make vivado
and then use iMPACT programming tool:
make ise-prog-fpga
to program the FPGA.
After successfully programmed the FPGA using the target 'ise-prog-fpga' user might
have to press the 'CPU RESET' button in order to successfully complete the calibration
process in the MIG. Led 1 and led 2 should be constant green if the Calibration
process has been successful.
If user tries to connect to the board and the MIG has not been calibrated successfully
'grmon' will output:
$ grmon -xilusb -u -nb
GRMON2 LEON debug monitor v2.0.43-2-g95d293c internal version
Copyright (C) 2013 Aeroflex Gaisler - All rights reserved.
For latest updates, go to http://www.gaisler.com/
Comments or bug-reports to support@gaisler.com
Parsing -xilusb
Parsing -u
Parsing -nb
Commands missing help:
datacache
Xilusb: Cable type/rev : 0x3
JTAG chain (1):
xc7vx485t
AMBA plug&play not found！
Failed to initialize target！
Exiting GRMON
The MIG and SGMII IP can be disabled either by deselecting the memory controller
and Gaisler Ethernet interface in 'xconfig' or manually editing the config.vhd file.
When no MIG and no SGMII block is present in the system normal GRLIB flow can be
used and no extra compile steps are needed. Also when when no MIG is present it
is possible to control and set the system frequency via xconfig.
Note that the system frequency can be modified via Vivado when the MIG is present
by modifying within specified limits for the MIG IP.
Compiling and launching modelsim when no memory controller and no ethernet interface
is present using Modelsim/Aldec simulator:
make vsim
make soft
make vsim-launch
Simulation options
------------------
All options are set either by editing the testbench or specify/modify the generic
default value when launching the simulator. For Modelsim use the option "-g" i.e.
to enable processor disassembly to console launch modelsim with the option: "-gdisas=1"
USE_MIG_INTERFACE_MODEL - Use MIG simulation model for faster simulation run time
(Option can now be controlled via 'make xconfig')
disas - Enable processor disassembly to console
DEBUG - Enable extra debug information when using Micron DDR3 models
Design specifics
----------------
* Synthesis should be done using Vivado 2014.4.1 or newer
* The DDR3 controller is implemented with Xilinx MIG 7-Series 2.0 and
runs of the 200 MHz clock. The DDR3 memory runs at 400 MHz
(DDR3-800). grmon-2.0.30-74 or later is needed to detect the
DDR3 memory.
* The AHB clock is generated by the MMCM module in the DDR3
controller, and can be controlled via Vivado. When the
MIG DDR3 controller isn't present the AHB clock is generated
from CLKGEN, and can be controlled via xconfig
* System reset is mapped to the CPU RESET button
* DSU break is mapped to GPIO east button
* LED 0 indicates processor in debug mode
* LED 1 indicates processor in error mode, execution halted
* LED 2 indicates DDR3 PHY initialization done (Only valid when MIG is present)
* LED 3 indicates internal PLL has locked (Only valid when MIG isn't present)
* 16-bit flash prom can be read at address 0. It can be programmed
with GRMON version 2.0.30-74 or later.
* The application UART1 is connected to the USB/RS232 connector if
switch 5, located on the DIP Switch SW2 of the board, is set to OFF.
* The AHB UART can be enabled by setting switch 5 to ON.
Since the board is equipped with one USB/RS232 connector, APB UART1 and
AHB UART cannot be used at the same time.
* The JTAG DSU interface is enabled and accesible via the JTAG port.
Start grmon with -xilusb to connect.
* Output from GRMON is:
grmon -xilusb
GRMON2 LEON debug monitor v2.0.30-149-ga91ee12 internal version
Copyright (C) 2012 Aeroflex Gaisler - All rights reserved.
For latest updates, go to http://www.gaisler.com/
Comments or bug-reports to support@gaisler.com
Parsing -xilusb
Xilusb: Cable type/rev : 0x3
JTAG chain (1): xc7vx485t
Commands missing help:
debug
GRLIB build version: 4118
Detected frequency: 100 MHz
Component Vendor
LEON3 SPARC V8 Processor Aeroflex Gaisler
AHB Debug UART Aeroflex Gaisler
JTAG Debug Link Aeroflex Gaisler
LEON2 Memory Controller European Space Agency
AHB/APB Bridge Aeroflex Gaisler
LEON3 Debug Support Unit Aeroflex Gaisler
Single-port AHB SRAM module Aeroflex Gaisler
Unknown device Aeroflex Gaisler
Single-port AHB SRAM module Aeroflex Gaisler
Generic UART Aeroflex Gaisler
Multi-processor Interrupt Ctrl. Aeroflex Gaisler
Modular Timer Unit Aeroflex Gaisler
AMBA Wrapper for OC I2C-master Aeroflex Gaisler
General Purpose I/O port Aeroflex Gaisler
Use command 'info sys' to print a detailed report of attached cores
grmon2> info sys
cpu0 Aeroflex Gaisler LEON3 SPARC V8 Processor
AHB Master 0
ahbuart0 Aeroflex Gaisler AHB Debug UART
AHB Master 1
APB: 80000700 - 80000800
Baudrate 115200, AHB frequency 100.00 MHz
ahbjtag0 Aeroflex Gaisler JTAG Debug Link
AHB Master 2
mctrl0 European Space Agency LEON2 Memory Controller
AHB: 00000000 - 20000000
APB: 80000000 - 80000100
16-bit prom @ 0x00000000
apbmst0 Aeroflex Gaisler AHB/APB Bridge
AHB: 80000000 - 80100000
dsu0 Aeroflex Gaisler LEON3 Debug Support Unit
AHB: 90000000 - A0000000
AHB trace: 256 lines, 32-bit bus
CPU0: win 8, hwbp 2, itrace 256, V8 mul/div, srmmu, lddel 1
stack pointer 0x20000ff0
icache 4 * 8 kB, 32 B/line dir
dcache 4 * 8 kB, 32 B/line dir
ahbram0 Aeroflex Gaisler Single-port AHB SRAM module
AHB: 20000000 - 20100000
32-bit static ram: 4 kB @ 0x20000000
adev7 Aeroflex Gaisler Unknown device
AHB: 40000000 - 48000000
APB: 80000400 - 80000500
ahbram1 Aeroflex Gaisler Single-port AHB SRAM module
AHB: A0000000 - A0100000
32-bit static ram: 4 kB @ 0xa0000000
uart0 Aeroflex Gaisler Generic UART
APB: 80000100 - 80000200
IRQ: 2
Baudrate 38343
irqmp0 Aeroflex Gaisler Multi-processor Interrupt Ctrl.
APB: 80000200 - 80000300
gptimer0 Aeroflex Gaisler Modular Timer Unit
APB: 80000300 - 80000400
IRQ: 8
8-bit scalar, 2 * 32-bit timers, divisor 100
i2cmst0 Aeroflex Gaisler AMBA Wrapper for OC I2C-master
APB: 80000800 - 80000900
IRQ: 11
gpio0 Aeroflex Gaisler General Purpose I/O port
APB: 80000A00 - 80000B00
grmon2> load systest.exe
40000000 .text 112.2kB / 112.2kB [===============>] 100%
40020000 .data 163.1kB / 163.1kB [===============>] 100%
Total size: 275.28kB (1.19Mbit/s)
Entry point 0x40000000
Image /home/ringhage/grlib_git/designs/leon3-xilinx-vc707/systest.exe loaded
grmon2> verify systest.exe
40000000 .text 112.2kB / 112.2kB [===============>] 100%
40020000 .data 163.1kB / 163.1kB [===============>] 100%
Total size: 275.28kB (85.23kbit/s)
Entry point 0x40000000
Image of /home/ringhage/grlib_git/designs/leon3-xilinx-vc707/systest.exe verified without errors
grmon2>
* grmon output using Ethernet
grmon -eth -ip 192.168.0.51 -u -nb
GRMON2 LEON debug monitor v2.0.33-88-g17c6483 internal version
Copyright (C) 2012 Aeroflex Gaisler - All rights reserved.
For latest updates, go to http://www.gaisler.com/
Comments or bug-reports to support@gaisler.com
Parsing -eth
Parsing -ip 192.168.0.51
Parsing -u
Parsing -nb
Commands missing help:
debug
datacache
Ethernet startup...
GRLIB build version: 4129
Detected frequency: 100 MHz
Component Vendor
LEON3 SPARC V8 Processor Aeroflex Gaisler
AHB Debug UART Aeroflex Gaisler
JTAG Debug Link Aeroflex Gaisler
GR Ethernet MAC Aeroflex Gaisler
USB Debug Communication Link Aeroflex Gaisler
LEON2 Memory Controller European Space Agency
AHB/APB Bridge Aeroflex Gaisler
LEON3 Debug Support Unit Aeroflex Gaisler
Single-port AHB SRAM module Aeroflex Gaisler
Xilinx MIG DDR3 Controller Aeroflex Gaisler
Single-port AHB SRAM module Aeroflex Gaisler
Generic UART Aeroflex Gaisler
Multi-processor Interrupt Ctrl. Aeroflex Gaisler
Modular Timer Unit Aeroflex Gaisler
AMBA Wrapper for OC I2C-master Aeroflex Gaisler
General Purpose I/O port Aeroflex Gaisler
Unknown device Aeroflex Gaisler
Use command 'info sys' to print a detailed report of attached cores
grmon2> info sys
cpu0 Aeroflex Gaisler LEON3 SPARC V8 Processor
AHB Master 0
ahbuart0 Aeroflex Gaisler AHB Debug UART
AHB Master 1
APB: 80000700 - 80000800
Baudrate 115200, AHB frequency 100.00 MHz
ahbjtag0 Aeroflex Gaisler JTAG Debug Link
AHB Master 2
greth0 Aeroflex Gaisler GR Ethernet MAC
AHB Master 3
APB: 80000E00 - 80000F00
IRQ: 12
1000 Mbit capable
edcl ip 192.168.0.51, buffer 2 kbyte
adev4 Aeroflex Gaisler USB Debug Communication Link
AHB Master 4
mctrl0 European Space Agency LEON2 Memory Controller
AHB: 00000000 - 20000000
APB: 80000000 - 80000100
16-bit prom @ 0x00000000
apbmst0 Aeroflex Gaisler AHB/APB Bridge
AHB: 80000000 - 80100000
dsu0 Aeroflex Gaisler LEON3 Debug Support Unit
AHB: 90000000 - A0000000
AHB trace: 256 lines, 32-bit bus
CPU0: win 8, hwbp 2, itrace 256, V8 mul/div, srmmu, lddel 1
stack pointer 0x7ffffff0
icache 4 * 4 kB, 32 B/line dir
dcache 4 * 4 kB, 32 B/line dir
ahbram0 Aeroflex Gaisler Single-port AHB SRAM module
AHB: 20000000 - 20100000
32-bit static ram: 4 kB @ 0x20000000
mig0 Aeroflex Gaisler Xilinx MIG DDR3 Controller
AHB: 40000000 - 80000000
APB: 80000400 - 80000500
SDRAM: 1024 Mbyte
ahbram1 Aeroflex Gaisler Single-port AHB SRAM module
AHB: A0000000 - A0100000
32-bit static ram: 4 kB @ 0xa0000000
uart0 Aeroflex Gaisler Generic UART
APB: 80000100 - 80000200
IRQ: 2
Baudrate 38343
irqmp0 Aeroflex Gaisler Multi-processor Interrupt Ctrl.
APB: 80000200 - 80000300
gptimer0 Aeroflex Gaisler Modular Timer Unit
APB: 80000300 - 80000400
IRQ: 8
8-bit scalar, 2 * 32-bit timers, divisor 100
i2cmst0 Aeroflex Gaisler AMBA Wrapper for OC I2C-master
APB: 80000900 - 80000A00
IRQ: 11
gpio0 Aeroflex Gaisler General Purpose I/O port
APB: 80000A00 - 80000B00
adev16 Aeroflex Gaisler Unknown device
APB: 80000B00 - 80000C00
grmon2> load /usr/local32/apps/bench/leon3/dhry.leon3
40000000 .text 54.7kB / 54.7kB [===============>] 100%
4000DAF0 .data 2.7kB / 2.7kB [===============>] 100%
Total size: 57.44kB (17.43Mbit/s)
Entry point 0x40000000
Image /usr/local32/apps/bench/leon3/dhry.leon3 loaded
grmon2> run
Execution starts, 1000000 runs through Dhrystone
Total execution time: 4.6 s
Microseconds for one run through Dhrystone: 4.6
Dhrystones per Second: 217085.5
Dhrystones MIPS : 123.6
Program exited normally.
grmon2> exit
* grmon output using digilent
grmon -digilent -u
GRMON2 LEON debug monitor v2.0.33-88-g17c6483 internal version
Copyright (C) 2012 Aeroflex Gaisler - All rights reserved.
For latest updates, go to http://www.gaisler.com/
Comments or bug-reports to support@gaisler.com
Parsing -digilent
Parsing -u
Commands missing help:
debug
datacache
JTAG chain (1): xc7vx485t
GRLIB build version: 4129
Detected frequency: 100 MHz
Component Vendor
LEON3 SPARC V8 Processor Aeroflex Gaisler
AHB Debug UART Aeroflex Gaisler
JTAG Debug Link Aeroflex Gaisler
GR Ethernet MAC Aeroflex Gaisler
USB Debug Communication Link Aeroflex Gaisler
LEON2 Memory Controller European Space Agency
AHB/APB Bridge Aeroflex Gaisler
LEON3 Debug Support Unit Aeroflex Gaisler
Single-port AHB SRAM module Aeroflex Gaisler
Xilinx MIG DDR3 Controller Aeroflex Gaisler
Single-port AHB SRAM module Aeroflex Gaisler
Generic UART Aeroflex Gaisler
Multi-processor Interrupt Ctrl. Aeroflex Gaisler
Modular Timer Unit Aeroflex Gaisler
AMBA Wrapper for OC I2C-master Aeroflex Gaisler
General Purpose I/O port Aeroflex Gaisler
Unknown device Aeroflex Gaisler
Use command 'info sys' to print a detailed report of attached cores
grmon2> info sys
cpu0 Aeroflex Gaisler LEON3 SPARC V8 Processor
AHB Master 0
ahbuart0 Aeroflex Gaisler AHB Debug UART
AHB Master 1
APB: 80000700 - 80000800
Baudrate 115200, AHB frequency 100.00 MHz
ahbjtag0 Aeroflex Gaisler JTAG Debug Link
AHB Master 2
greth0 Aeroflex Gaisler GR Ethernet MAC
AHB Master 3
APB: 80000E00 - 80000F00
IRQ: 12
1000 Mbit capable
edcl ip 192.168.0.51, buffer 2 kbyte
adev4 Aeroflex Gaisler USB Debug Communication Link
AHB Master 4
mctrl0 European Space Agency LEON2 Memory Controller
AHB: 00000000 - 20000000
APB: 80000000 - 80000100
16-bit prom @ 0x00000000
apbmst0 Aeroflex Gaisler AHB/APB Bridge
AHB: 80000000 - 80100000
dsu0 Aeroflex Gaisler LEON3 Debug Support Unit
AHB: 90000000 - A0000000
AHB trace: 256 lines, 32-bit bus
CPU0: win 8, hwbp 2, itrace 256, V8 mul/div, srmmu, lddel 1
stack pointer 0x7ffffff0
icache 4 * 4 kB, 32 B/line dir
dcache 4 * 4 kB, 32 B/line dir
ahbram0 Aeroflex Gaisler Single-port AHB SRAM module
AHB: 20000000 - 20100000
32-bit static ram: 4 kB @ 0x20000000
mig0 Aeroflex Gaisler Xilinx MIG DDR3 Controller
AHB: 40000000 - 80000000
APB: 80000400 - 80000500
SDRAM: 1024 Mbyte
ahbram1 Aeroflex Gaisler Single-port AHB SRAM module
AHB: A0000000 - A0100000
32-bit static ram: 4 kB @ 0xa0000000
uart0 Aeroflex Gaisler Generic UART
APB: 80000100 - 80000200
IRQ: 2
Baudrate 38343
irqmp0 Aeroflex Gaisler Multi-processor Interrupt Ctrl.
APB: 80000200 - 80000300
gptimer0 Aeroflex Gaisler Modular Timer Unit
APB: 80000300 - 80000400
IRQ: 8
8-bit scalar, 2 * 32-bit timers, divisor 100
i2cmst0 Aeroflex Gaisler AMBA Wrapper for OC I2C-master
APB: 80000900 - 80000A00
IRQ: 11
gpio0 Aeroflex Gaisler General Purpose I/O port
APB: 80000A00 - 80000B00
adev16 Aeroflex Gaisler Unknown device
APB: 80000B00 - 80000C00
grmon2>
* grmon output using USB debug link
sudo grmon -usb -nb -u
GRMON2 LEON debug monitor v2.0.33-88-g17c6483 internal version
Copyright (C) 2012 Aeroflex Gaisler - All rights reserved.
For latest updates, go to http://www.gaisler.com/
Comments or bug-reports to support@gaisler.com
Parsing -usb
Parsing -nb
Parsing -u
Commands missing help:
debug
datacache
GRLIB build version: 4129
Detected frequency: 100 MHz
Component Vendor
LEON3 SPARC V8 Processor Aeroflex Gaisler
AHB Debug UART Aeroflex Gaisler
JTAG Debug Link Aeroflex Gaisler
GR Ethernet MAC Aeroflex Gaisler
USB Debug Communication Link Aeroflex Gaisler
LEON2 Memory Controller European Space Agency
AHB/APB Bridge Aeroflex Gaisler
LEON3 Debug Support Unit Aeroflex Gaisler
Single-port AHB SRAM module Aeroflex Gaisler
Xilinx MIG DDR3 Controller Aeroflex Gaisler
Single-port AHB SRAM module Aeroflex Gaisler
Generic UART Aeroflex Gaisler
Multi-processor Interrupt Ctrl. Aeroflex Gaisler
Modular Timer Unit Aeroflex Gaisler
AMBA Wrapper for OC I2C-master Aeroflex Gaisler
General Purpose I/O port Aeroflex Gaisler
Unknown device Aeroflex Gaisler
Use command 'info sys' to print a detailed report of attached cores
grmon2> load /usr/local32/apps/bench/leon3/dhry.leon3
40000000 .text 54.7kB / 54.7kB [===============>] 100%
4000DAF0 .data 2.7kB / 2.7kB [===============>] 100%
Total size: 57.44kB (24.77Mbit/s)
Entry point 0x40000000
Image /usr/local32/apps/bench/leon3/dhry.leon3 loaded
grmon2> verify /usr/local32/apps/bench/leon3/dhry.leon3
40000000 .text 54.7kB / 54.7kB [===============>] 100%
4000DAF0 .data 2.7kB / 2.7kB [===============>] 100%
Total size: 57.44kB (13.84Mbit/s)
Entry point 0x40000000
Image of /usr/local32/apps/bench/leon3/dhry.leon3 verified without errors
grmon2> run
Execution starts, 1000000 runs through Dhrystone
Total execution time: 4.6 s
Microseconds for one run through Dhrystone: 4.6
Dhrystones per Second: 216215.1
Dhrystones MIPS : 123.1
Program exited normally.
grmon2>
Note: This design requires that the GRLIB_SIMULATOR variable iscorrectly set. Please refer to the documentation in doc/grlib.pdf for
additional information.
Note: The Vivado flow and parts of this design are still
experimental. Currently the design configuration should be left as-is.
Note: You must have Vivado 2014.4.1 in your path for the make targets to work.
The XILINX_VIVADO variable must be exported for the mig_7series target
to work correctly: export XILINX_VIVADO
Simulation and synthesis
------------------------
The design uses the Xilinx MIG memory interface with an AHB-2.0
interface and Xilinx SGMII PHY Interface. The MIG or the SGMII PHY
source code cannot be distributed due to the prohibitive Xilinx
license, so the MIG and/or the SGMII must be re-generated with
Vivado before simulation and synthesis can be done.
Xilinx MIG and SGMII interface will automatically be generated when
Vivado is launched
To simulate using XSIM and run systest.c on the Leon design using the memory
controller from Xilinx use the make targets:
make soft
make vivado-launch
To simulate using Modelsim/Aldec and run systest.c on the Leon design using
the memory controller from Xilinx use the make targets:
make map_xilinx_7series_lib
make sim
make mig_7series
make sgmii_7series
make sim-launch
To simulate using the Aldec Riviera WS flow use the following make targets:
make riviera_ws # creates riviera workspace
make map_xilinx_7series_lib # compiles and maps xilinx sim libs
make mig_7series # generates MIG IP and adds to riviera project
make sgmii_7series # same for SGMII adapter
make riviera # compile full project
make riviera-launch # launch simulation
To synthesize the design, do
make vivado
and then use iMPACT programming tool:
make ise-prog-fpga
to program the FPGA.
//大概给了这么一个说明，但是就是跑不通
你好，最近也在搞leon3的xilinx FPGA移植，跑不通，软件下载不进去，你的搞好了吗?
加油加油
你好，最近也在搞leon3的FPGA移植，你的搞好了吗?方便留个联系方式交流下吗
FPGA开发 V7的话 Vivado工具就可以了
用虚拟机对性能有影响，要么都在linux，要么都在windows下
建个工程 代码放进去 fpga选好，建个ucf 管脚对着电路图 设好，生成bit file ，烧到fpga里
你好，你搞过这个Leon3在xilinx-vc-707上么?能否请教下，跑仿真跑不过，提示 library unsim not found，但是以及知行make install-unsim命令了；我用的软件是，Linux下的ISE 14.7，仿真用的modelsim。
777777777777777
没有移植过，帮顶
222222222222222