什么是soc DV testbench

不知上下文是什麼? 我猜是 design verification

应该是design verification的意思，我之前以为是某种testbench的术语。
We are currently looking for engineer who will be responsible for design verification of cutting edge GPU projects. Qualified candidate will participate in and lead SoC level function verification domains including:
1.        SoC DV testbench and infrastructure development and maintenance
2.        Create and execute SoC testplan including data-path and interrupt, virtualization, security, power management, etc.
3.        Implement directed and random test cases in C++/SV, as well as checkers and assertions
4.        Support integration and qualification of all the IPs for SoC
5.        Help to improve DV environment building flow