ISE综合过了，MAP提示slice不够，但实际上slice应该是够的，求解答
软件：Synplify pro 2012.03;ISE 14.2器件：spartant6系列的xc6slx100-3fgg484
问题描述：有三个模块，分别命名为A,B,C；单独的模块资源A>B>C，其中A，B的资源差不多且远大于C的资源。进行设计时出现以下现象：
1.A+B的时候，综合、MAP均没问题
2.A+C的时候，综合、MAP均没问题
3.B+C和时候，综合没问题，MAP却提示：ERRORlace:543 - This design does not fit into the number of slices available
in this device due to the complexity of the design and/or constraints.
4.A+B+C，使用ISE10.1,器件选择spartan3A-DSP系列的XC3SD3400A（该器件的资源比上述器件要少得多），综合和MAP均没问题。
从逻辑上分析，上述第3种情况不应该会有问题，求大神解答这是什么原因，该如何解决?谢谢！
上述第１种情况synplify的综合报告如下：
---------------------------------------
Resource Usage Report for G001_TOP
Mapping to part: xc6slx100fgg484-3
Cell usage:
BUF 48 uses
DCM_SP 1 use
DSP48A 30 uses
DSP48A1 124 uses
FD 264 uses
FDC 6997 uses
FDCE 8987 uses
FDE 891 uses
FDP 61 uses
FDPE 136 uses
FDR 178 uses
FDRE 1286 uses
FDRSE 162 uses
FDSE 38 uses
GND 338 uses
Latch-Through 221 uses
LDC 6 uses
MUXCY 1380 uses
MUXCY_L 6223 uses
MUXF5 1077 uses
MUXF6 520 uses
MUXF7 1246 uses
MUXF8 253 uses
RAM16X1D 4220 uses
RAM32M 128 uses
RAM32X1D 16 uses
RAMB16BWER 73 uses
RAMB8BWER 5 uses
VCC 338 uses
XORCY 6577 uses
LUT1 2009 uses
LUT2 8342 uses
LUT3 4689 uses
LUT4 3488 uses
LUT5 1668 uses
LUT6 5504 uses
LUT6_2 3 uses
I/O ports: 122
I/O primitives: 118
IBUF 34 uses
IBUFG 1 use
IOBUF 32 uses
OBUF 50 uses
ODDR2 1 use
BUFG 10 uses
SRL primitives:
SRLC16E 64 uses
SRLC32E 64 uses
SRL16 4 uses
SRL16E 488 uses
I/O Register bits: 0
Register bits not including I/Os: 19000 (13%)
Latch bits not including I/Os: 6 (0%)
RAM/ROM usage summary
Dual Port Rams (RAM16X1D): 4220
Dual Port Rams (RAM32X1D): 16
Simple Dual Port Rams (RAM32M): 128
Block Rams : 78 of 268 (29%)
DSP48s: 154 of 180 (85%)
Global Clock Buffers: 10 of 16 (62%)
Total load per clock:
G001_CLK_GEN|clk_1m08_derived_clock: 14493
G001_UL_AB_NB_RX|nb_crc_valid_derived_clock: 2
G001_UL_AB_NB_RX|ab_crc_valid_derived_clock: 2
CLK_GEN|CLK0_BUF_derived_clock: 7380
CLK_GEN|CLKFX_BUF_derived_clock: 774
Inital|cnt_clk26m_dv_derived_clock[3]: 112
Inital|cnt_clk26m_dv_derived_clock[4]: 170
Inital|cnt_clk26m_dv_derived_clock[7]: 78
G001_CLK_GEN|r_count_derived_clock[2]: 406
CLK_GEN|CLKDV_BUF_derived_clock: 5
G001_TOP|i_clk26m: 1
Mapping Summary:
Total LUTs: 32343 (46%)
Distribution of All Consumed LUTs = SRL + RAM + LUT1 + LUT2 + LUT3 + LUT4 + LUT5 + LUT6 + LUT6_2- HLUTNM/2
Distribution of All Consumed Luts 32343 = 620 + 8984 + 2009 + 8342 + 4689 + 3488 + 1668 + 5504 + 3- 5928/2
Number of unique control sets: 347
Mapper successful！
At Mapper Exit (Time elapsed 0h:06m:59s; Memory used current: 144MB peak: 425MB)
Process took 0h:07m:10s realtime, 0h:06m:59s cputime
# Mon Mar 04 22:45:17 2013
###########################################################]
上术第2种情况的综合报告如下：
---------------------------------------
Resource Usage Report for G001_TOP
Mapping to part: xc6slx100fgg484-3
Cell usage:
BUF 45 uses
DCM_SP 1 use
DSP48A 42 uses
DSP48A1 59 uses
FD 267 uses
FDC 2191 uses
FDCE 7733 uses
FDE 887 uses
FDP 79 uses
FDPE 115 uses
FDR 184 uses
FDRE 1304 uses
FDRSE 162 uses
FDSE 40 uses
GND 311 uses
Latch-Through 130 uses
MUXCY 850 uses
MUXCY_L 3757 uses
MUXF5 1067 uses
MUXF6 516 uses
MUXF7 1003 uses
MUXF8 233 uses
RAM16X1D 4220 uses
RAM32M 80 uses
RAMB16BWER 70 uses
RAMB8BWER 3 uses
VCC 311 uses
XORCY 3963 uses
LUT1 1587 uses
LUT2 2640 uses
LUT3 4187 uses
LUT4 1941 uses
LUT5 945 uses
LUT6 3492 uses
LUT6_2 2 uses
I/O ports: 122
I/O primitives: 118
IBUF 34 uses
IBUFG 1 use
IOBUF 32 uses
OBUF 50 uses
ODDR2 1 use
BUFG 11 uses
SRL primitives:
SRLC16E 64 uses
SRLC32E 33 uses
SRL16 4 uses
SRL16E 507 uses
I/O Register bits: 0
Register bits not including I/Os: 12962 (9%)
RAM/ROM usage summary
Dual Port Rams (RAM16X1D): 4220
Simple Dual Port Rams (RAM32M): 80
Block Rams : 73 of 268 (27%)
DSP48s: 101 of 180 (56%)
Global Clock Buffers: 11 of 16 (68%)
Total load per clock:
G001_CLK_GEN|clk_1m08_derived_clock: 11135
G001_TXv4|package_tx_done_flag_derived_clock: 65
CLK_GEN|CLKFX_BUF_derived_clock: 774
Inital|cnt_clk26m_dv_derived_clock[3]: 112
CLK_GEN|CLK0_BUF_derived_clock: 4446
Inital|cnt_clk26m_dv_derived_clock[4]: 170
Inital|cnt_clk26m_dv_derived_clock[7]: 78
G001_CLK_GEN|r_count_derived_clock[2]: 406
CLK_GEN|CLKDV_BUF_derived_clock: 5
G001_TOP|i_clk26m: 1
Mapping Summary:
Total LUTs: 23550 (34%)
Distribution of All Consumed LUTs = SRL + RAM + LUT1 + LUT2 + LUT3 + LUT4 + LUT5 + LUT6 + LUT6_2- HLUTNM/2
Distribution of All Consumed Luts 23550 = 608 + 8760 + 1587 + 2640 + 4187 + 1941 + 945 + 3492 + 2- 1224/2
Number of unique control sets: 315
Mapper successful！
At Mapper Exit (Time elapsed 0h:04m:24s; Memory used current: 107MB peak: 286MB)
Process took 0h:04m:32s realtime, 0h:04m:24s cputime
# Tue Mar 05 08:39:52 2013
###########################################################]
上述第3种情况的综合报告如下：
---------------------------------------
Resource Usage Report for G001_TOP
Mapping to part: xc6slx100fgg484-3
Cell usage:
BUF 30 uses
DCM_SP 1 use
DSP48A 42 uses
DSP48A1 83 uses
FD 280 uses
FDC 6153 uses
FDCE 3945 uses
FDE 859 uses
FDP 60 uses
FDPE 133 uses
FDR 70 uses
FDRE 1304 uses
FDRSE 162 uses
FDSE 40 uses
GND 316 uses
Latch-Through 91 uses
LDC 6 uses
MUXCY 938 uses
MUXCY_L 4497 uses
MUXF5 1066 uses
MUXF6 516 uses
MUXF7 851 uses
MUXF8 224 uses
RAM16X1D 4220 uses
RAM32M 48 uses
RAM32X1D 16 uses
RAMB16BWER 65 uses
RAMB8BWER 4 uses
VCC 316 uses
XORCY 4709 uses
LUT1 1682 uses
LUT2 7244 uses
LUT3 3683 uses
LUT4 2571 uses
LUT5 1103 uses
LUT6 3260 uses
LUT6_2 4 uses
I/O ports: 122
I/O primitives: 118
IBUF 34 uses
IBUFG 1 use
IOBUF 32 uses
OBUF 50 uses
ODDR2 1 use
BUFG 8 uses
SRL primitives:
SRLC16E 40 uses
SRLC32E 33 uses
SRL16 4 uses
SRL16E 495 uses
I/O Register bits: 0
Register bits not including I/Os: 13006 (9%)
Latch bits not including I/Os: 6 (0%)
RAM/ROM usage summary
Dual Port Rams (RAM16X1D): 4220
Dual Port Rams (RAM32X1D): 16
Simple Dual Port Rams (RAM32M): 48
Block Rams : 69 of 268 (25%)
DSP48s: 125 of 180 (69%)
Global Clock Buffers: 8 of 16 (50%)
Total load per clock:
G001_CLK_GEN|r_clk_1m08_derived_clock: 10625
G001_TXv4|package_tx_done_flag_derived_clock: 65
G001_UL_AB_NB_RX|ab_crc_valid_derived_clock: 3
G001_UL_AB_NB_RX|nb_crc_valid_derived_clock: 3
CLK_GEN|CLK0_BUF_derived_clock: 6167
CLK_GEN|CLKFX_BUF_derived_clock: 774
Inital|cnt_clk26m_dv_derived_clock[3]: 112
Inital|cnt_clk26m_dv_derived_clock[4]: 170
Inital|cnt_clk26m_dv_derived_clock[7]: 78
CLK_GEN|CLKDV_BUF_derived_clock: 1
G001_TOP|i_clk26m: 1
Mapping Summary:
Total LUTs: 26068 (37%)
Distribution of All Consumed LUTs = SRL + RAM + LUT1 + LUT2 + LUT3 + LUT4 + LUT5 + LUT6 + LUT6_2- HLUTNM/2
Distribution of All Consumed Luts 26068 = 572 + 8664 + 1682 + 7244 + 3683 + 2571 + 1103 + 3260 + 4- 5430/2
Number of unique control sets: 262
Mapper successful！
At Mapper Exit (Time elapsed 0h:04m:14s; Memory used current: 115MB peak: 367MB)
Process took 0h:04m:19s realtime, 0h:04m:14s cputime
# Tue Mar 05 09:53:49 2013
###########################################################]
ISE的MAP报告：
Release 14.2 Map P.28xd (nt)
Xilinx Mapping Report File for Design 'G001_TOP'
Design Information
------------------
Command Line : map -intstyle ise -p xc6slx100-fgg484-3 -w -logic_opt off -ol
high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off
-detail -ir off -pr b -lc off -power off -o G001_TOP_map.ncd G001_TOP.ngd
G001_TOP.pcf
Target Device : xc6slx100
Target Package : fgg484
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Tue Mar 05 14:31:13 2013
Interim Summary
---------------
Slice Logic Utilization:
Number of Slice Registers: 12,660 out of 126,576 10%
Number used as Flip Flops: 12,651
Number used as Latches: 6
Number used as Latch-thrus: 0
Number used as AND/OR logics: 3
Number of Slice LUTs: 24,504 out of 63,288 38%
Number used as logic: 15,295 out of 63,288 24%
Number using O6 output only: 10,427
Number using O5 output only: 390
Number using O5 and O6: 4,478
Number used as ROM: 0
Number used as Memory: 8,966 out of 15,616 57%
Number used as Dual Port RAM: 8,536
Number using O6 output only: 8,224
Number using O5 output only: 96
Number using O5 and O6: 216
Number used as Single Port RAM: 0
Number used as Shift Register: 430
Number using O6 output only: 249
Number using O5 output only: 40
Number using O5 and O6: 141
Number used exclusively as route-thrus: 243
Number with same-slice register load: 0
Number with same-slice carry load: 135
Number with other load: 108
Slice Logic Distribution:
Nummber of MUXCYs used: 6,572 out of 31,644 20%
Number of LUT Flip Flop pairs used: 28,133
Number with an unused Flip Flop: 17,760 out of 28,133 63%
Number with an unused LUT: 3,629 out of 28,133 12%
Number of fully used LUT-FF pairs: 6,744 out of 28,133 23%
Number of unique control sets: 509
Number of slice register sites lost
to control set restrictions: 1,484 out of 126,576 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 117 out of 326 35%
IOB Flip Flops: 109
Specific Feature Utilization:
Number of RAMB16BWERs: 65 out of 268 24%
Number of RAMB8BWERs: 4 out of 536 1%
Number of BUFIO2/BUFIO2_2CLKs: 1 out of 32 3%
Number used as BUFIO2s: 1
Number used as BUFIO2_2CLKs: 0
Number of BUFIO2FB/BUFIO2FB_2CLKs: 1 out of 32 3%
Number used as BUFIO2FBs: 1
Number used as BUFIO2FB_2CLKs: 0
Number of BUFG/BUFGMUXs: 8 out of 16 50%
Number used as BUFGs: 8
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 1 out of 12 8%
Number used as DCMs: 1
Number used as DCM_CLKGENs: 0
Number of ILOGIC2/ISERDES2s: 60 out of 506 11%
Number used as ILOGIC2s: 60
Number used as ISERDES2s: 0
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 506 0%
Number of OLOGIC2/OSERDES2s: 49 out of 506 9%
Number used as OLOGIC2s: 49
Number used as OSERDES2s: 0
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 384 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 125 out of 180 69%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 4 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 0 out of 6 0%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Design Summary
--------------
Number of errors : 5
Number of warnings : 81
Section 1 - Errors
------------------
ERRORlace:543 - This design does not fit into the number of slices available
in this device due to the complexity of the design and/or constraints.
Unplaced instances by type:
FF 42 (2.0)
LUTM 368 (4.5)
Please evaluate the following:
- If there are user-defined constraints or area groups:
Please look at the "User-defined constraints" section below to determine
what constraints might be impacting the fitting of this design.
Evaluate if they can be moved, removed or resized to allow for fitting.
Verify that they do not overlap or conflict with clock region restrictions.
See the clock region reports in the MAP log file (*map) for more details
on clock region usage.
- If there is difficulty in placing LUTs:
Try using the MAP LUT Combining Option (map lc area|auto|off).
- If there is difficulty in placing FFs:
Evaluate the number and configuration of the control sets in your design.
The following instances are the last set of instances that failed to place:
0. G001_TX_DFE2/G001_txdfe_HB_q/blk00000003/sig00000077 (size: 6)
LUTM G001_TX_DFE2/G001_txdfe_HB_q/blk00000003/sig00000077
LUTM G001_TX_DFE2/G001_txdfe_HB_q/blk00000003/blk0000002f/blk00000032
LUTM G001_TX_DFE2/G001_txdfe_HB_q/blk00000003/sig00000077
LUTM G001_TX_DFE2/G001_txdfe_HB_q/blk00000003/blk00000034/blk00000037
FF G001_TX_DFE2/G001_txdfe_HB_q/blk00000003/blk0000002f/blk00000033
FF G001_TX_DFE2/G001_txdfe_HB_q/blk00000003/blk00000034/blk00000038
1. G001_TX_DFE2/G001_txdfe_HB_i/blk00000003/sig00000077 (size: 6)
LUTM G001_TX_DFE2/G001_txdfe_HB_i/blk00000003/sig00000077
LUTM G001_TX_DFE2/G001_txdfe_HB_i/blk00000003/blk0000002f/blk00000032
LUTM G001_TX_DFE2/G001_txdfe_HB_i/blk00000003/sig00000077
LUTM G001_TX_DFE2/G001_txdfe_HB_i/blk00000003/blk00000034/blk00000037
FF G001_TX_DFE2/G001_txdfe_HB_i/blk00000003/blk0000002f/blk00000033
FF G001_TX_DFE2/G001_txdfe_HB_i/blk00000003/blk00000034/blk00000038
。（省略）
99. NB_DUT_FIFO/BU2/U0.grf.rf.mem.gdm.dm.N3521 (size: 4)
LUTM NB_DUT_FIFO/BU2/U0.grf.rf.mem.gdm.dm.N3521
LUTM NB_DUT_FIFO/BU2/U0.grf.rf.mem.gdm.dm.Mram_RAM1696/SP
LUTM NB_DUT_FIFO/BU2/U0.grf.rf.mem.gdm.dm.N3521
LUTM NB_DUT_FIFO/BU2/U0.grf.rf.mem.gdm.dm.Mram_RAM1696/DP
ERRORlace:543 - This design does not fit into the number of slices available
in this device due to the complexity of the design and/or constraints.
Unplaced instances by type:
（ 以下类似，省略）
会不会是报告上说的原因：due to the complexity of the design and/or constraints?
由于设计复杂度比较高，同时约束又比较多，所以无法完成布局布线?而不仅仅是资源的原因?
具体出错的信息有没?
重点检查下B与C之间可能共有的资源，比如PIN脚冲突、时钟资源冲突等，比如是否用到BUFR资源，且同时驱动两模块?BUFG资源的产生和使用，有没有一些信号用到ILOGIC里的寄存器的，也就是IOB相关的冲突?SLICE相关的话，有没有过于复杂的逻辑?约束，先把约束去掉看看，或者有没有位置约束?指定某些资源固定位置的去掉。
谢谢你的答复。要说复杂度，约束，如上面描述的第４种情况，用低版本的ISE,资源少的器件却可以。
A B C三个模块是相互独立的，没有逻辑上的联系。我把所有的约束都去掉了，运行结果还是一样的。如果我换成同系列资源多一点的器件xc6slx150，则可以map通过，且从结果来看，所使用的资源并没有超过xc6slx100的资源，事实上基本上不超过５０%。
Release 14.2 Map P.28xd (nt)Xilinx Mapping Report File for Design 'G001_TOP'
Design Information
------------------
Command Line : map -intstyle ise -p xc6slx100-fgg484-3 -w -logic_opt off -ol
high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off
-detail -ir off -pr b -lc off -power off -o G001_TOP_map.ncd G001_TOP.ngd
G001_TOP.pcf
Target Device : xc6slx100
Target Package : fgg484
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Tue Mar 05 14:31:13 2013
Interim Summary
---------------
Slice Logic Utilization:
Number of Slice Registers: 12,660 out of 126,576 10%
Number used as Flip Flops: 12,651
Number used as Latches: 6
Number used as Latch-thrus: 0
Number used as AND/OR logics: 3
Number of Slice LUTs: 24,504 out of 63,288 38%
Number used as logic: 15,295 out of 63,288 24%
Number using O6 output only: 10,427
Number using O5 output only: 390
Number using O5 and O6: 4,478
Number used as ROM: 0
Number used as Memory: 8,966 out of 15,616 57%
Number used as Dual Port RAM: 8,536
Number using O6 output only: 8,224
Number using O5 output only: 96
Number using O5 and O6: 216
Number used as Single Port RAM: 0
Number used as Shift Register: 430
Number using O6 output only: 249
Number using O5 output only: 40
Number using O5 and O6: 141
Number used exclusively as route-thrus: 243
Number with same-slice register load: 0
Number with same-slice carry load: 135
Number with other load: 108
Slice Logic Distribution:
Nummber of MUXCYs used: 6,572 out of 31,644 20%
Number of LUT Flip Flop pairs used: 28,133
Number with an unused Flip Flop: 17,760 out of 28,133 63%
Number with an unused LUT: 3,629 out of 28,133 12%
Number of fully used LUT-FF pairs: 6,744 out of 28,133 23%
Number of unique control sets: 509
Number of slice register sites lost
to control set restrictions: 1,484 out of 126,576 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 117 out of 326 35%
IOB Flip Flops: 109
Specific Feature Utilization:
Number of RAMB16BWERs: 65 out of 268 24%
Number of RAMB8BWERs: 4 out of 536 1%
Number of BUFIO2/BUFIO2_2CLKs: 1 out of 32 3%
Number used as BUFIO2s: 1
Number used as BUFIO2_2CLKs: 0
Number of BUFIO2FB/BUFIO2FB_2CLKs: 1 out of 32 3%
Number used as BUFIO2FBs: 1
Number used as BUFIO2FB_2CLKs: 0
Number of BUFG/BUFGMUXs: 8 out of 16 50%
Number used as BUFGs: 8
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 1 out of 12 8%
Number used as DCMs: 1
Number used as DCM_CLKGENs: 0
Number of ILOGIC2/ISERDES2s: 60 out of 506 11%
Number used as ILOGIC2s: 60
Number used as ISERDES2s: 0
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 506 0%
Number of OLOGIC2/OSERDES2s: 49 out of 506 9%
Number used as OLOGIC2s: 49
Number used as OSERDES2s: 0
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 384 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 125 out of 180 69%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 4 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 0 out of 6 0%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Design Summary
--------------
Number of errors : 5
Number of warnings : 81
Section 1 - Errors
------------------
ERRORlace:543 - This design does not fit into the number of slices available
in this device due to the complexity of the design and/or constraints.
Unplaced instances by type:
FF 42 (2.0)
LUTM 368 (4.5)
Please evaluate the following:
- If there are user-defined constraints or area groups:
Please look at the "User-defined constraints" section below to determine
what constraints might be impacting the fitting of this design.
Evaluate if they can be moved, removed or resized to allow for fitting.
Verify that they do not overlap or conflict with clock region restrictions.
See the clock region reports in the MAP log file (*map) for more details
on clock region usage.
- If there is difficulty in placing LUTs:
Try using the MAP LUT Combining Option (map lc area|auto|off).
- If there is difficulty in placing FFs:
Evaluate the number and configuration of the control sets in your design.
The following instances are the last set of instances that failed to place:
0. G001_TX_DFE2/G001_txdfe_HB_q/blk00000003/sig00000077 (size: 6)
LUTM G001_TX_DFE2/G001_txdfe_HB_q/blk00000003/sig00000077
LUTM G001_TX_DFE2/G001_txdfe_HB_q/blk00000003/blk0000002f/blk00000032
LUTM G001_TX_DFE2/G001_txdfe_HB_q/blk00000003/sig00000077
LUTM G001_TX_DFE2/G001_txdfe_HB_q/blk00000003/blk00000034/blk00000037
FF G001_TX_DFE2/G001_txdfe_HB_q/blk00000003/blk0000002f/blk00000033
FF G001_TX_DFE2/G001_txdfe_HB_q/blk00000003/blk00000034/blk00000038
1. G001_TX_DFE2/G001_txdfe_HB_i/blk00000003/sig00000077 (size: 6)
LUTM G001_TX_DFE2/G001_txdfe_HB_i/blk00000003/sig00000077
LUTM G001_TX_DFE2/G001_txdfe_HB_i/blk00000003/blk0000002f/blk00000032
LUTM G001_TX_DFE2/G001_txdfe_HB_i/blk00000003/sig00000077
LUTM G001_TX_DFE2/G001_txdfe_HB_i/blk00000003/blk00000034/blk00000037
FF G001_TX_DFE2/G001_txdfe_HB_i/blk00000003/blk0000002f/blk00000033
FF G001_TX_DFE2/G001_txdfe_HB_i/blk00000003/blk00000034/blk00000038
。（省略）
99. NB_DUT_FIFO/BU2/U0.grf.rf.mem.gdm.dm.N3521 (size: 4)
LUTM NB_DUT_FIFO/BU2/U0.grf.rf.mem.gdm.dm.N3521
LUTM NB_DUT_FIFO/BU2/U0.grf.rf.mem.gdm.dm.Mram_RAM1696/SP
LUTM NB_DUT_FIFO/BU2/U0.grf.rf.mem.gdm.dm.N3521
LUTM NB_DUT_FIFO/BU2/U0.grf.rf.mem.gdm.dm.Mram_RAM1696/DP
ERRORlace:543 - This design does not fit into the number of slices available
in this device due to the complexity of the design and/or constraints.
Unplaced instances by type:
（ 以下类似，省略）
这是map报错后的报告
从资源上来看，也没用到很多
Release 14.2 Map P.28xd (nt)
Xilinx Mapping Report File for Design 'G001_TOP'
Design Information
------------------
Command Line : map -intstyle ise -p xc6slx100-fgg484-3 -w -logic_opt off -ol
high -xe n -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off
-detail -ir off -pr b -lc off -power off -o G001_TOP_map.ncd G001_TOP.ngd
G001_TOP.pcf
Target Device : xc6slx100
Target Package : fgg484
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Tue Mar 05 14:31:13 2013
Interim Summary
---------------
Slice Logic Utilization:
Number of Slice Registers: 12,660 out of 126,576 10%
Number used as Flip Flops: 12,651
Number used as Latches: 6
Number used as Latch-thrus: 0
Number used as AND/OR logics: 3
Number of Slice LUTs: 24,504 out of 63,288 38%
Number used as logic: 15,295 out of 63,288 24%
Number using O6 output only: 10,427
Number using O5 output only: 390
Number using O5 and O6: 4,478
Number used as ROM: 0
Number used as Memory: 8,966 out of 15,616 57%
Number used as Dual Port RAM: 8,536
Number using O6 output only: 8,224
Number using O5 output only: 96
Number using O5 and O6: 216
Number used as Single Port RAM: 0
Number used as Shift Register: 430
Number using O6 output only: 249
Number using O5 output only: 40
Number using O5 and O6: 141
Number used exclusively as route-thrus: 243
Number with same-slice register load: 0
Number with same-slice carry load: 135
Number with other load: 108
Slice Logic Distribution:
Nummber of MUXCYs used: 6,572 out of 31,644 20%
Number of LUT Flip Flop pairs used: 28,133
Number with an unused Flip Flop: 17,760 out of 28,133 63%
Number with an unused LUT: 3,629 out of 28,133 12%
Number of fully used LUT-FF pairs: 6,744 out of 28,133 23%
Number of unique control sets: 509
Number of slice register sites lost
to control set restrictions: 1,484 out of 126,576 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 117 out of 326 35%
IOB Flip Flops: 109
Specific Feature Utilization:
Number of RAMB16BWERs: 65 out of 268 24%
Number of RAMB8BWERs: 4 out of 536 1%
Number of BUFIO2/BUFIO2_2CLKs: 1 out of 32 3%
Number used as BUFIO2s: 1
Number used as BUFIO2_2CLKs: 0
Number of BUFIO2FB/BUFIO2FB_2CLKs: 1 out of 32 3%
Number used as BUFIO2FBs: 1
Number used as BUFIO2FB_2CLKs: 0
Number of BUFG/BUFGMUXs: 8 out of 16 50%
Number used as BUFGs: 8
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 1 out of 12 8%
Number used as DCMs: 1
Number used as DCM_CLKGENs: 0
Number of ILOGIC2/ISERDES2s: 60 out of 506 11%
Number used as ILOGIC2s: 60
Number used as ISERDES2s: 0
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 506 0%
Number of OLOGIC2/OSERDES2s: 49 out of 506 9%
Number used as OLOGIC2s: 49
Number used as OSERDES2s: 0
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 384 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 125 out of 180 69%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 4 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 0 out of 6 0%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Design Summary
--------------
Number of errors : 5
Number of warnings : 81
Section 1 - Errors
------------------
ERRORlace:543 - This design does not fit into the number of slices available
in this device due to the complexity of the design and/or constraints.
Unplaced instances by type:
FF 42 (2.0)
LUTM 368 (4.5)
Please evaluate the following:
- If there are user-defined constraints or area groups:
Please look at the "User-defined constraints" section below to determine
what constraints might be impacting the fitting of this design.
Evaluate if they can be moved, removed or resized to allow for fitting.
Verify that they do not overlap or conflict with clock region restrictions.
See the clock region reports in the MAP log file (*map) for more details
on clock region usage.
- If there is difficulty in placing LUTs:
Try using the MAP LUT Combining Option (map lc area|auto|off).
- If there is difficulty in placing FFs:
Evaluate the number and configuration of the control sets in your design.
The following instances are the last set of instances that failed to place:
0. G001_TX_DFE2/G001_txdfe_HB_q/blk00000003/sig00000077 (size: 6)
LUTM G001_TX_DFE2/G001_txdfe_HB_q/blk00000003/sig00000077
LUTM G001_TX_DFE2/G001_txdfe_HB_q/blk00000003/blk0000002f/blk00000032
LUTM G001_TX_DFE2/G001_txdfe_HB_q/blk00000003/sig00000077
LUTM G001_TX_DFE2/G001_txdfe_HB_q/blk00000003/blk00000034/blk00000037
FF G001_TX_DFE2/G001_txdfe_HB_q/blk00000003/blk0000002f/blk00000033
FF G001_TX_DFE2/G001_txdfe_HB_q/blk00000003/blk00000034/blk00000038
1. G001_TX_DFE2/G001_txdfe_HB_i/blk00000003/sig00000077 (size: 6)
LUTM G001_TX_DFE2/G001_txdfe_HB_i/blk00000003/sig00000077
LUTM G001_TX_DFE2/G001_txdfe_HB_i/blk00000003/blk0000002f/blk00000032
LUTM G001_TX_DFE2/G001_txdfe_HB_i/blk00000003/sig00000077
LUTM G001_TX_DFE2/G001_txdfe_HB_i/blk00000003/blk00000034/blk00000037
FF G001_TX_DFE2/G001_txdfe_HB_i/blk00000003/blk0000002f/blk00000033
FF G001_TX_DFE2/G001_txdfe_HB_i/blk00000003/blk00000034/blk00000038
。（省略）
99. NB_DUT_FIFO/BU2/U0.grf.rf.mem.gdm.dm.N3521 (size: 4)
LUTM NB_DUT_FIFO/BU2/U0.grf.rf.mem.gdm.dm.N3521
LUTM NB_DUT_FIFO/BU2/U0.grf.rf.mem.gdm.dm.Mram_RAM1696/SP
LUTM NB_DUT_FIFO/BU2/U0.grf.rf.mem.gdm.dm.N3521
LUTM NB_DUT_FIFO/BU2/U0.grf.rf.mem.gdm.dm.Mram_RAM1696/DP
ERRORlace:543 - This design does not fit into the number of slices available
in this device due to the complexity of the design and/or constraints.
Unplaced instances by type:
（ 以下类似，省略）
已经贴出来了，麻烦帮忙看一下，谢谢
你地方找错了，
Design Summary
--------------
Number of errors : 5
Number of warnings : 81
Section 1 - Errors
------------------
ERRORlace:543 - This design does not fit into the number of slices available
in this device due to the complexity of the design and/or constraints.
这里已经总结性地告诉你error了，且有5个，应找上面这段更上面出现ERROR信息，直接搜索ERROR就可，那才是原始错误信息。
问题已经解决了，是由于使用的工程是由ISE直接从旧的版本工程移植过来的，里面使用的IP是旧的版本且针对原来旧的器件，把IP核重新配置生成后就可以了。谢谢各位的意见！
原来又是IP核的问题，换芯片一般记得重新生成IP核，不然还是有潜在风险的。
我也遇到同样的问题，按您说的解决不错误，还有别的问题吗?
不錯的資料 真的很實用 謝謝分享
把ncd文件删掉
我的一直都是14.7工程，直接复制的，怎么也是这样，跟你的问题一样，我的怎么解决啊，求教啊！