Xilinx ISE 在MAP的时候总在PLace的时候报错 时钟引脚分配的问题
时间：10-02
整理：3721RD
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抱错如下：
ERRORlace:293 - The following 2 components are required to be placed in a specific
relative placement form. The required relative coordinates in the RPM grid (that can be
seen in the FPGA Editor) are shown in brackets next to the component names. Due to
placement constraints it is impossible to place the components in the required form.
ERRORlace:645 - A clock IOB clock component is not placed at an optimal clock
IOB site. The clock IOB component <CLK_61M_W> is placed at site <IOB_X1Y103>.
The clock IO site can use the fast path between the IO and the Clock
buffer/GCLK if the IOB is placed in the master Clock IOB Site. If this sub
optimal condition is acceptable for this design, you may use the
CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a
WARNING and allow your design to continue. However, the use of this override
is highly discouraged as it may lead to very poor timing results. It is
recommended that this error condition be corrected in the design. A list of
all the COMP.PINs used in this clock placement rule is listed below. These
examples can be used directly in the .ucf file to override this clock rule.
< NET "CLK_61M_W" CLOCK_DEDICATED_ROUTE = FALSE; >
ERRORack:1654 - The timing-driven placement phase encountered an error.
根据抱错的提示，在UCF文件中加入了NET "CLK_61M_W" CLOCK_DEDICATED_ROUTE = FALSE; 约束语句，但是还是有错误的呀，求各位指导一下
软件版的版本是12.4 m8.1
求讨论，求指导，小弟菜鸟一只，刚刚入门呀。
ERRORlace:293 - The following 2 components are required to be placed in a specific
relative placement form. The required relative coordinates in the RPM grid (that can be
seen in the FPGA Editor) are shown in brackets next to the component names. Due to
placement constraints it is impossible to place the components in the required form.
ERRORlace:645 - A clock IOB clock component is not placed at an optimal clock
IOB site. The clock IOB component <CLK_61M_W> is placed at site <IOB_X1Y103>.
The clock IO site can use the fast path between the IO and the Clock
buffer/GCLK if the IOB is placed in the master Clock IOB Site. If this sub
optimal condition is acceptable for this design, you may use the
CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a
WARNING and allow your design to continue. However, the use of this override
is highly discouraged as it may lead to very poor timing results. It is
recommended that this error condition be corrected in the design. A list of
all the COMP.PINs used in this clock placement rule is listed below. These
examples can be used directly in the .ucf file to override this clock rule.
< NET "CLK_61M_W" CLOCK_DEDICATED_ROUTE = FALSE; >
ERRORack:1654 - The timing-driven placement phase encountered an error.
根据抱错的提示，在UCF文件中加入了NET "CLK_61M_W" CLOCK_DEDICATED_ROUTE = FALSE; 约束语句，但是还是有错误的呀，求各位指导一下
软件版的版本是12.4 m8.1
求讨论，求指导，小弟菜鸟一只，刚刚入门呀。
这个正常情况下加到UCF里面就可以解决了。再查查UCF是不是加对了。另外，整个流程要重头开始，不能只重做map.
谢谢你的回复，
但是我确实在UCF文件中已经加入了
NET "CLK_61M_W" CLOCK_DEDICATED_ROUTE = FALSE;
这一点是百分之百无问题的，
而且在运行的时候，我每次都是用的是Rerun All
所以所有的process都是冲头开始的，
把引号去掉试试看?
谢谢你的回复，
我试了你给的方法，
但是，没用啊，好像还是那样的错误
ise中的引脚分为几种，有的是适合clock的，有些是适合组合逻辑的。第二个错误应该是你那个引脚本应该是一个clock引脚，需要分配到GC pin上面，但是你分配到了CC或者其它的引脚上面了，不过如果不想换引脚位置，可以在RTL里面通过Global buffer来转换下。GC pin一般是用于连接clock的。第一个就不知道了~
第一个错误，看样子是过约束导致的，你检查下相关错误所在的位置，是不是使用了过严的约束，要不先把约束注释掉再看看。
第二个问题，你所用的CLOCK PIN是不是DATA PIN，并不适合作为时钟使用的?上面说IOB输入离CLOCK BUFFER太远，一般情况下，作为CLOCK PIN的输入后应很快就能找到CLOCK BUFFER资源的，要么换个PIN试试，要么先加个IBUFG，再BUFG，或者先IBUFG，再DCM，再BUFG出去。
层主真是大神啊，现在绝对是 FPGA 的先驱者了
很好的帖子，谢谢