请教一个verilog问题，谢谢！

时间：10-02 整理：3721RD 点击：

`ifdef D3D_SYNC_RESET
always @(posedge clk_core) begin
`else
always @(posedge clk_core or negedge rst_x) begin
`endif
if (rst_x == `D3D_RESET_POL) begin
r_state <= IDLE;
end else begin
case (r_state)
IDLE: begin
if (i_en) r_state <= LINE_0;
end
LINE_0: begin
if (i | w_reject_l0) r_state <= LINE_1;
end
LINE_1: begin
if (i | w_reject_l1) r_state <= LINE_2;
end
LINE_2: begin
if (i | w_reject_l2) r_state <= IDLE;
end
endcase
end
end

复制代码

请教下，这个里面的`ifdef,他是到`endif结束呢?还是把下面状态机运行完呢?假设D3D_SYNC_RESET已定义。谢谢！

ifdef与c语言中的含义一样，这里你假设D3D_SYNC_RESET已定义那么代码将变成
always @(posedge clk_core) begin
  if (rst_x == `D3D_RESET_POL) begin
r_state <= IDLE;
  end else begin
case (r_state)
   IDLE: begin
      if (i_en) r_state <= LINE_0;
   end
   LINE_0: begin
      if (i | w_reject_l0) r_state <= LINE_1;
   end
   LINE_1: begin
      if (i | w_reject_l1) r_state <= LINE_2;
   end
   LINE_2: begin
      if (i | w_reject_l2) r_state <= IDLE;
   end
endcase
  end
end
而不是你想的状态机运不运行的问题，与这个无关

懂了，谢谢！

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