Xilinx K7系列中OSERDES的问题
100MHz钟-->MMCM-->(CLK=500MHz钟,CLK_div=250MHz钟)-->OSERDES(DDR,4:1,并行数据=4'b1010)-->500MHz数据时钟输出
用ISIM做功能仿真正确，但implement后的时序仿真输出数据时钟始终不变(恒定为0)，不知道到底怎么回事?麻烦高手指点迷津，谢谢！源码如下
`timescale 1ns/1ps
module TOP_DESIGN
(
input clk_in,
input reset_pll,
input reset_serdes,
output mmcm_lock,
output CLK_TO_PINS_P,
output CLK_TO_PINS_N
);
wire clkfbout;
wire clkout0;
wire clkout1;
wire clkfbout_buf;
wire clkin1;
wire highspeed_clk;
wire lowspeed_clk;
reg IO_RESET;
reg [7:0] rst_dly;
wire oserdes_out;
MMCME2_ADV #
(
.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.divCLK_divIDE (1),
.CLKFBOUT_MULT_F (10.000),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_divIDE_F (2.000),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_divIDE (4.000),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (10.0),
.REF_JITTER1 (0.010)
)
U1_MMCM
( // Output clocks
.CLKFBOUT (clkfbout),
.CLKFBOUTB (),
.CLKOUT0 (clkout0),
.CLKOUT0B (),
.CLKOUT1 (clkout1),
.CLKOUT1B (),
.CLKOUT2 (),
.CLKOUT2B (),
.CLKOUT3 (),
.CLKOUT3B (),
.CLKOUT4 (),
.CLKOUT5 (),
.CLKOUT6 (),
// Input clock control
.CLKFBIN (clkfbout_buf),
.CLKIN1 (clkin1),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (),
.DRDY (),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (),
// Other control and status signals
.LOCKED (mmcm_lock),
.CLKINSTOPPED (),
.CLKFBSTOPPED (),
.PWRDWN (1'b0),
.RST (reset_pll)
);
BUFG U2_BUFG
(
.O (clkfbout_buf),
.I (clkfbout)
);
BUFG U3_BUFG
(
.O (highspeed_clk),
.I (clkout0)
);
BUFG U4_BUFG
(
.O (lowspeed_clk),
.I (clkout1)
);
IBUFG U5_BUFG
( .I (clk_in),
.O (clkin1)
);
OSERDESE2
#(
.DATA_RATE_OQ ("DDR"),
.DATA_RATE_TQ ("SDR"),
.DATA_WIDTH (4),
.TRISTATE_WIDTH (1),
.SERDES_MODE ("MASTER")
)
U6_SERDES
(
.D1 (1'b1),
.D2 (1'b0),
.D3 (1'b1),
.D4 (1'b0),
.D5 (1'b1),
.D6 (1'b0),
.D7 (1'b1),
.D8 (1'b0),
.T1 (1'b0),
.T2 (1'b0),
.T3 (1'b0),
.T4 (1'b0),
.SHIFTIN1 (1'b0),
.SHIFTIN2 (1'b0),
.SHIFTOUT1 (),
.SHIFTOUT2 (),
.OCE (rst_dly[4]),
.CLK (highspeed_clk),
.CLKdiv (lowspeed_clk),
.OQ (oserdes_out),
.TQ (),
.OFB (),
.TFB (),
.TBYTEIN (1'b0),
.TBYTEOUT (),
.TCE (1'b0),
.RST (IO_RESET)
);
OBUFDS
#(.IOSTANDARD ("LVDS"))
obufds_inst
(.O (CLK_TO_PINS_P),
.OB (CLK_TO_PINS_N),
.I (oserdes_out)
);
always @ (posedge lowspeed_clk or posedge reset_serdes)
begin
if(reset_serdes)
begin
IO_RESET <= 1'b1;
rst_dly <= 8'b0000_0000;
end
else
begin
IO_RESET <= 1'b0;
rst_dly[7:1] <= rst_dly[6:0];
rst_dly[0] <= 1'b1;
end
end
endmodule
器件是XC7K325T-2FFG900
再附上仿真用文件
`timescale
1 ns / 1 ps
module TOP_SIM();
localparam CLK100_PERIOD = 10; //in nSec
reg clk_in;
reg reset_pll;
reg reset_serdes;
wire mmcm_lock;
wire CLK_TO_PINS_P;
wire CLK_TO_PINS_N;
TOP_DESIGN
SIM (
.clk_in (clk_in),
.reset_pll (reset_pll),
.reset_serdes (reset_serdes),
.mmcm_lock (mmcm_lock),
.CLK_TO_PINS_P (CLK_TO_PINS_P),
.CLK_TO_PINS_N (CLK_TO_PINS_N)
);
// Stimulation Generation
initial
begin
reset_pll = 1'b1;
#200
reset_pll = 1'b0;
end
initial
begin
reset_serdes = 1'b1;
#1200
reset_serdes = 1'b0;
end
// Clock Generation
initial
clk_in = 1'b0;
always #(CLK100_PERIOD/2.0) clk_in = ~clk_in;
endmodule
你把数据接出来看看 数据正确否? 很可能模块都没有工作。
你好，我也在使用K7，有个问题请教下，MMCME2_ADV是原语还是模块或者是IP啊?
同问啊，这个MMCME2_ADV 是个啥，官网上下下来一个近4k行代码的这个module。都不知道他从哪里来的，干啥用的。
没用过oserderse，学习下
谢谢分享