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关于用verilog语言编写检测开关的问题

时间：10-02 整理：3721RD 点击：
如果现在一共有18个拨动开关，用什么样的办法检测被关闭的两个开关是哪?只要求测出最左和最右两端的开关。我自己的思路部分代码如下：

  1. input[17:0] rang;
  2. wire[17:0] rang_1;

  4. assign rang_1 ={rang[0], rang[1], rang[2],rang[3],rang[4],rang[5],rang[6],rang[7], rang[8],rang[9], rang[10],rang[11],rang[12],rang[13],rang[14],rang[15],rang[16],rang[17]};



  8. always @(posedge clk or negedge clr_n)

  10. if(！clr_n)

  12. left_temp <=5'd0;

  14. else

  16. casex(rang)

  18. 18'b1xxxxxxxxxxxxxxxxx:left_temp <= 5'd1;

  20. 18'b01xxxxxxxxxxxxxxxx:left_temp <= 5'd2;

  22. 18'b001xxxxxxxxxxxxxxx:left_temp <= 5'd3;

  24. 18'b0001xxxxxxxxxxxxxx:left_temp <= 5'd4;

  26. 18'b00001xxxxxxxxxxxxx:left_temp <= 5'd5;

  28. 18'b000001xxxxxxxxxxxx:left_temp <= 5'd6;

  30. 18'b0000001xxxxxxxxxxx:left_temp <= 5'd7;

  32. 18'b00000001xxxxxxxxxx:left_temp <= 5'd8;

  34. 18'b000000001xxxxxxxxx:left_temp <= 5'd9;

  36. 18'b0000000001xxxxxxxx:left_temp <= 5'd10;

  38. 18'b00000000001xxxxxxx:left_temp <= 5'd11;

  40. 18'b000000000001xxxxxx:left_temp <= 5'd12;

  42. 18'b0000000000001xxxxx:left_temp <= 5'd13;

  44. 18'b00000000000001xxxx:left_temp <= 5'd14;

  46. 18'b000000000000001xxx:left_temp <= 5'd15;

  48. 18'b0000000000000001xx:left_temp <= 5'd16;

  50. 18'b00000000000000001x:left_temp <= 5'd17;

  52. 18'b000000000000000001:left_temp <= 5'd18;

  54. default: left_temp <= 5'd0;

  56. endcase



  60. always @(posedge clk or negedge clr_n)

  62. if(！clr_n)

  64. right_temp <=5'd13;

  66. else

  68. casex(rang)

  70. 18'bxxxxxxxxxxxxxxxxx1:right_temp <= 5'd18;

  72. 18'bxxxxxxxxxxxxxxxx10:right_temp <= 5'd17;

  74. 18'bxxxxxxxxxxxxxxx100:right_temp <= 5'd16;

  76. 18'bxxxxxxxxxxxxxx1000:right_temp <= 5'd15;

  78. 18'bxxxxxxxxxxxxx10000:right_temp <= 5'd14;

  80. 18'bxxxxxxxxxxxx100000:right_temp <= 5'd13;

  82. 18'bxxxxxxxxxxx1000000:right_temp <= 5'd12;

  84. 18'bxxxxxxxxxx10000000:right_temp <= 5'd11;

  86. 18'bxxxxxxxxx100000000:right_temp <= 5'd10;

  88. 18'bxxxxxxxx1000000000:right_temp <= 5'd9;

  90. 18'bxxxxxxx10000000000:right_temp <= 5'd8;

  92. 18'bxxxxxx100000000000:right_temp <= 5'd7;

  94. 18'bxxxxx1000000000000:right_temp <= 5'd6;

  96. 18'bxxxx10000000000000:right_temp <= 5'd5;

  98. 18'bxxx100000000000000:right_temp <= 5'd4;

  100. 18'bxx1000000000000000:right_temp <= 5'd3;

  102. 18'bx10000000000000000:right_temp <= 5'd2;

  104. 18'b100000000000000000:right_temp <= 5'd1;

  106. default: right_temp <= 5'd19;

  108. endcase

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