VHDL和Verilog的区别
时间：10-02
整理：3721RD
点击：
1. Verilog is much easier to learn than VHDL
2. VHDL syntax is drived from Ada language, verilog syntax is drived from C language.
3. VHDL isa system level language, Verilog is a gate level language.
4. VHDL is a strongly type language, Verilog uses veak typing.
5. case sensitivity for Verilog, not for VHDL
2. VHDL syntax is drived from Ada language, verilog syntax is drived from C language.
3. VHDL isa system level language, Verilog is a gate level language.
4. VHDL is a strongly type language, Verilog uses veak typing.
5. case sensitivity for Verilog, not for VHDL