微波EDA网,见证研发工程师的成长!
首页 > 研发问答 > 嵌入式设计讨论 > FPGA,CPLD和ASIC > PhysDesignrule:10

PhysDesignrule:10

时间:10-02 整理:3721RD 点击:
我在windows下用synplify_pro生成.edf和.ucf,然后用ISE生成bit文件一切正常。最近在服务器上跑代码,服务器是linux系统,也装了synplify_pro,生成.edf和.ucf,然后拷到windows下,用ISE生成bit文件时,报下面的错误:
ERRORhysDesignRules:10 - The network
   <u_dm5601_fpga_inst/u_dm5601_fpga_top/u_Sample/u_DDR3/u_memc_ui_top_std/mem_i
   ntfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_p
   hy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/oserdes_clk_c> is completely
   unrouted.
ERRORhysDesignRules:10 - The network
   <u_dm5601_fpga_inst/u_dm5601_fpga_top/u_Sample/u_DDR3/u_memc_ui_top_std/mem_i
   ntfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_p
   hy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/oserdes_clk_c> is completely
   unrouted.
ERRORhysDesignRules:10 - The network
   <u_dm5601_fpga_inst/u_dm5601_fpga_top/u_Sample/u_DDR3/u_memc_ui_top_std/mem_i
   ntfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_p
   hy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/oserdes_clk_c> is completely
   unrouted.
ERROR:PhysDesignRules:10 - The network
   <u_dm5601_fpga_inst/u_dm5601_fpga_top/u_Sample/u_DDR3/u_memc_ui_top_std/mem_i
   ntfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_p
   hy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/oserdes_clk_c> is completely
   unrouted.
ERROR:PhysDesignRules:10 - The network
   <u_dm5601_fpga_inst/u_dm5601_fpga_top/u_Sample/u_DDR3/u_memc_ui_top_std/mem_i
   ntfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_p
   hy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/oserdes_clk_c> is completely
   unrouted.
ERROR:PhysDesignRules:10 - The network
   <u_dm5601_fpga_inst/u_dm5601_fpga_top/u_Sample/u_DDR3/u_memc_ui_top_std/mem_i
   ntfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_p
   hy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/oserdes_clk_c> is completely
   unrouted.
ERROR:PhysDesignRules:10 - The network
   <u_dm5601_fpga_inst/u_dm5601_fpga_top/u_Sample/u_DDR3/u_memc_ui_top_std/mem_i
   ntfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_p
   hy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/oserdes_clk_c> is completely
   unrouted.
ERROR:PhysDesignRules:10 - The network
   <u_dm5601_fpga_inst/u_dm5601_fpga_top/u_Sample/u_DDR3/u_memc_ui_top_std/mem_i
   ntfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_p
   hy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/oserdes_clk_c> is completely
   unrouted.
WARNING:PhysDesignRules:2487 - For MMCM_ADV block
   u_dm5601_fpga_inst/u_dm5601_fpga_top/u_Sample/u_DDR3/u_ddr3_infrastructure/ge
   n_mmcm.mmcm_i, the CLKOUT0_divIDE_F programming of <6.5024> is not supported.
   CLKOUT0_divIDE_F will be adjusted to the hardware granularity of a multiple
   of 0.125.
ERROR:Bitgen:25 - DRC detected 8 errors and 330 warnings.  Please see the
   previously displayed individual error or warning messages for more details.

不知道为什么.

Copyright © 2017-2020 微波EDA网 版权所有

网站地图

Top