ISE静态时序分析求助
could you point out a complete timing report ?
l'm sorry.i can't give you complete timing report. I just describe it to you.I need a clock at frequency 160MHz, but timing report says "component switching limit checks: NET "clk" PERIOD=6.25ns HIGH 50%.
slack: -0.304ns( max period limit - period ).
period: 6.25ns
Max period limit: 5.946ns (168.180MHz) (Tdcmpc)
您好，我有一个时序问题想咨询你，下面是我的timing report
--------------------------------------------------------------------------------
Release 14.7 Trace (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
D:\xilinxISE147\14.7\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -e 1
-nodatasheet -s 2 -n 1000 -fastpaths -xml MainCore.twx MainCore.ncd -o
MainCore.twr MainCore.pcf -ucf MainCore.ucf
Design file: MainCore.ncd
Physical constraint file: MainCore.pcf
Device,package,speed: xc6slx4,tqg144,C,-2 (PRODUCTION 1.23 2013-10-13)
Report level: error report, limited to 1 item per endpoint, 1000 endpoints per constraint
Environment Variable Effect
-------------------- ------
NONE No environment variables were set
--------------------------------------------------------------------------------
INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
a 50 Ohm transmission line loading model. For the details of this model,
and for more information on accounting for different loading conditions,
please see the device datasheet.
================================================================================
Timing constraint: TS_FOSC = PERIOD TIMEGRP "FOSC" 4 MHz HIGH 50%;
For more information, see Period Analysis in the Timing Closure User Guide (UG612).
190 paths analyzed, 59 endpoints analyzed, 0 failing endpoints
3 timing errors detected. (0 setup errors, 0 hold errors, 3 component switching limit errors)
Minimum period is 80.000ns.
--------------------------------------------------------------------------------
Component Switching Limit Checks: TS_FOSC = PERIOD TIMEGRP "FOSC" 4 MHz HIGH 50%;
--------------------------------------------------------------------------------
Slack: -50.000ns (max period limit - period)
Period: 250.000ns
Max period limit: 200.000ns (5.000MHz) (Tdcmper_CLKIN)
Physical resource: i_ClockDistrib/i_DFS1/CLKIN
Logical resource: i_ClockDistrib/i_DFS1/CLKIN
Location pin: DCM_X0Y1.CLKIN
Clock network: i_ClockDistrib/i_DFS1_ML_NEW_divCLK
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TS_i_ClockDistrib_FOS8M = PERIOD TIMEGRP "i_ClockDistrib_FOS8M" TS_FOSC * 2 HIGH 50%;
For more information, see Period Analysis in the Timing Closure User Guide (UG612).
252 paths analyzed, 102 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
Minimum period is 4.918ns.
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TS_i_ClockDistrib_ClkDFS1Int = PERIOD TIMEGRP "i_ClockDistrib_ClkDFS1Int" TS_FOSC * 16 HIGH 50%;
For more information, see Period Analysis in the Timing Closure User Guide (UG612).
30370 paths analyzed, 2278 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
Minimum period is 11.878ns.
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TS_i_ClockDistrib_FOS4M = PERIOD TIMEGRP "i_ClockDistrib_FOS4M" TS_FOSC HIGH 50%;
For more information, see Period Analysis in the Timing Closure User Guide (UG612).
464332726530 paths analyzed, 449 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
Minimum period is 135.440ns.
--------------------------------------------------------------------------------
Derived Constraint Report
Derived Constraints for TS_FOSC
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period | Timing Errors | Paths Analyzed |
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_FOSC | 250.000ns| 80.000ns| 190.048ns| 3| 0| 190| 464332757152|
| TS_i_ClockDistrib_FOS8M | 125.000ns| 4.918ns| N/A| 0| 0| 252| 0|
| TS_i_ClockDistrib_ClkDFS1Int | 15.625ns| 11.878ns| N/A| 0| 0| 30370| 0|
| TS_i_ClockDistrib_FOS4M | 250.000ns| 135.440ns| N/A| 0| 0| 464332726530| 0|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
1 constraint not met.
Timing summary:
---------------
Timing errors: 3 Score: 125000 (Setup/Max: 0, Hold: 0, Component Switching Limit: 125000)
Constraints cover 464332757342 paths, 0 nets, and 8395 connections
Design statistics:
Minimum period: 135.440ns (Maximum frequency: 7.383MHz)
Analysis completed Mon Apr 25 14:30:41 2016
--------------------------------------------------------------------------------
Trace Settings:
-------------------------
Trace Settings
Peak Memory Usage: 241 MB
你这个是slack值为负嘛，跟我的不一样哦。