新人求助，modelsim出现warning，没有结果，懂的朋友可以指点一下吗？

我用的是quartus，我在工程中调用了lpm ip核，用quartus仿真没问题，但用modelsim仿真出现错误，错误如下
# Warning : Address pointed at port A is out of bound！
# Time: 750  Instance: viterbi_test.i1.dRam1.altsyncram_component
# Warning : Address pointed at port A is out of bound！
# Time: 770  Instance: viterbi_test.i1.dRam1.altsyncram_component
# Warning : Address pointed at port A is out of bound！
# Time: 1490  Instance: viterbi_test.i1.dRam2.altsyncram_component
# Warning : Address pointed at port A is out of bound！
# Time: 1510  Instance: viterbi_test.i1.dRam2.altsyncram_component
# Warning : Address pointed at port A is out of bound！
# Time: 1670  Instance: viterbi_test.i1.dRam1.altsyncram_component
# Warning : Address pointed at port A is out of bound！
# Time: 2230  Instance: viterbi_test.i1.dRam3.altsyncram_component
# Warning : Address pointed at port A is out of bound！
# Time: 2250  Instance: viterbi_test.i1.dRam3.altsyncram_component
# Warning : Address pointed at port A is out of bound！
# Time: 2390  Instance: viterbi_test.i1.dRam2.altsyncram_component
# Warning : Address pointed at port A is out of bound！
# Time: 2390  Instance: viterbi_test.i1.dRam2.altsyncram_component
# Warning : Address pointed at port A is out of bound！
# Time: 2970  Instance: viterbi_test.i1.dRam1.altsyncram_component
# Warning : Address pointed at port A is out of bound！
# Time: 2990  Instance: viterbi_test.i1.dRam1.altsyncram_component
# Warning : Address pointed at port A is out of bound！
# Time: 3110  Instance: viterbi_test.i1.dRam3.altsyncram_component
# Warning : Address pointed at port A is out of bound！
# Time: 3110  Instance: viterbi_test.i1.dRam3.altsyncram_component
# Warning : Address pointed at port A is out of bound！
# Time: 3710  Instance: viterbi_test.i1.dRam2.altsyncram_component
# Warning : Address pointed at port A is out of bound！
# Time: 3730  Instance: viterbi_test.i1.dRam2.altsyncram_component
# Warning : Address pointed at port A is out of bound！
# Time: 3830  Instance: viterbi_test.i1.dRam1.altsyncram_component
# Warning : Address pointed at port A is out of bound！
# Time: 3830  Instance: viterbi_test.i1.dRam1.altsyncram_component
# Warning : Address pointed at port A is out of bound！
# Time: 4450  Instance: viterbi_test.i1.dRam3.altsyncram_component
# Warning : Address pointed at port A is out of bound！
# Time: 4470  Instance: viterbi_test.i1.dRam3.altsyncram_component
# Warning : Address pointed at port A is out of bound！
# Time: 4550  Instance: viterbi_test.i1.dRam2.altsyncram_component
# Warning : Address pointed at port A is out of bound！
# Time: 4550  Instance: viterbi_test.i1.dRam2.altsyncram_component

这是工程中的相关代码
dRam dRam1 (.clock(clk),.wren(wrRamEnable1),.address(ramAddress1),.data(dataInRamTemp),.q(dataOutRamTemp1));
dRam dRam2 (.clock(clk),.wren(wrRamEnable2),.address(ramAddress2),.data(dataInRamTemp),.q(dataOutRamTemp2));
dRam dRam3 (.clock(clk),.wren(wrRamEnable3),.address(ramAddress3),.data(dataInRamTemp),.q(dataOutRamTemp3));

我感觉是第三方软件没有识别ip核，导致出错，希望有经验的大牛可以帮解答一下，谢谢了。

没有人知道吗，我重新写了一个ram，没用lpm，就过了。哦，另外仿真前的初始化也很重要，否则会输出高阻态。

应该是LPM的仿真库没加进去导致的吧！

第一怀疑仿真库不全

你模块里面Bus定义的数位和你给的不一致吧， 比如address可能定义为【7：0】， 外面给的是【8：0】

你的第三方IP的库没有加进去。导致例化的ram没有正常工作